281 chapter 9 watch timer 9.4 watch timer interrupt when the interval time is reac hed with the watch ti mer interrupt enabled, the overflow flag bit is set to 1 and an in terrupt request is generated. watch timer interrupt table 9.4-1 shows the interrupt control bits and interrupt factors of the watch timer. when the value set by the interval time select bits (wtc2 to wtc0) in the watch timer control register (wtc) is reached, the overflow flag bit in th e wtc register is set to 1 (wtc: wtof = 1). when the overflow flag bit is set (wtc: wtof = 1) with the watch timer interrupt enabled (wtc: wtie = 1), an interrupt request is generated. at interrupt processing, set the wtof b it to 0 and cancel the interrupt request. watch timer interrupt and ei 2 os function the watch timer does not correspond to the ei 2 os function. for details of the interrupt number, interrupt contro l register, and interrupt v ector address, see section "3.5 interrupt". table 9.4-1 interrupt control bits of watch timer watch timer interrupt factor interval time of watch timer counter interrupt request flag bit wtc: wtof (overflow flag bit) interrupt factor enable bit wtc: wtie .com .com .com .com 4 .com u datasheet
282 chapter 9 watch timer 9.5 explanation of operation of watch timer the watch timer operates as an interval timer or an oscillation stabi lization wait time timer of subclock. it al so supplies an operation cl ock to the watchdog timer. watch timer counter the watch timer counter continues incrementing in synchronization with the subclock (sclk) while the subclock (sclk) is operating. clearing watch timer counter the watch timer counter is cleared to "0000 h " when: a power-on reset occurs. the mode transits to the stop mode. the watch timer clear bit (wtr) in the watch timer control register (wtc) is set to 0. interval timer function the watch timer can be used as an interval timer by generating an interr upt at each in terval time. settings when using watch timer as interval timer operating the watch timer as an interval timer requires the settings shown in figure 9.5-1. figure 9.5-1 setting of watch timer when the value set by the interval time select bits (wtc1, wtc0) in the watch timer control register (wtc) is reached, the overflow flag bit in th e wtc register is set to 1 (wtc: wtof = 1). when the overflow flag bit is set (wtc: wtof = 1) with the overflow interrupt of the watch timer counter enabled (wtc: wtie = 1), an interrupt request is generated. the overflow flag bit (wtc: wtof) is set when the interval time is reached at the starting point of the timing at which the watch timer is finally cleared. note: when the watch timer counter is cleared, the interr upts of the watchdog timer and interval timer that use the output of the watch timer counter are affected. to clear the watch timer by writing zero to the watch timer clear bit (wtr) in the watch timer control register (wtc), set the overflow interrupt enable bit (wtie) to "0" and set the watch timer to interrupt inhibited state. before permitting an interrupt, clear the interrupt request issued by writing zero to the overflow flag bit (wtof) in the wtc register. : used bit x: undefined bit7654321bit0 wtc wdcs sce wtie wtof wtr wtc2 wtc1 wtc0 xx .com .com .com .com 4 .com u datasheet
283 chapter 9 watch timer clearing overflow flag bit (wtc: wtof) when the mode is switched to the stop mode, the watc h timer is used as an oscillation stabilization wait time timer of subclock. the wtof bit is cl eared concurrently w ith mode switching. setting operation clock of watchdog timer the watchdog clock select bit (wdcs) in the watch tim er control register (wtc) can be used to set the clock input source of the watchdog timer. when using the subclock as the machine clock, always set the wdcs bit to 0 and select the output of the watch timer. oscillation stabilization wa it time timer of subclock when the watch timer returns from the power-on rese t and the stop mode, it functions as an oscillation stabilization wait time timer of subclock. the subclock oscillation stabilization wait time is fixed at 2 14 /sclk (sclk: subclock frequency). .com .com .com .com 4 .com u datasheet
284 chapter 9 watch timer 9.6 program example of watch timer this section gives a program example of the watch timer. program example of watch timer processing specifications an interval interrupt at 2 13 /sclk (sclk: subclock) is generated repeatedly. the interval time is approximately 1.0s (when subclock operates at 8.192 khz). coding example icr07 equ 0000b7h ; interrupt control register wtc equ 0000aah ; watch timer control register wtof equ wtc:4 ; overflow flag bit ; ;-----main program--------------------------------------------------------------- code cseg start: ; : ; stack pointer (sp) already initialized and ccr,#0bfh ; interrupt disabled mov i:icr07,#00h ; interrupt level 0 (highest) mov i:wtc, #10100101b ; interrupt enabled ; overflow flag bit cleared ; watch timer counter cleared ; 2 13 /sclk (approx. 1.0 s) mov ilm,#07h ; ilm in ps set to level 7 or ccr,#40h ; interrupt enabled loop: . processing by user . bra loop ;-----interrupt program---------------------------------------------------------- wari: clrb i:wtof ; overflow flag cleared . processing by user . reti ; return from interrupt processing code ends ;-----vector setting------------------------------------------------------------- vect cseg abs=0ffh org 00ff 8 ch ; vector set to interrupt #2 8 (1ch) dsl wari org 00ffdch ; reset vector set dsl start db 00h ; set to single-chip mode vect ends end start .com .com .com .com 4 .com u datasheet
285 chapter 10 8-/16-bit ppg timer this section describes the functions and operations of the 8-/16-bit ppg timer. 10.1 overview of 8-/16-bit ppg timer 10.2 block diagram of 8-/16-bit ppg timer 10.3 configuration of 8-/16-bit ppg timer 10.4 interrupts of 8-/16-bit ppg timer 10.5 explanation of operation of 8-/16-bit ppg timer 10.6 precautions when using 8-/16-bit ppg timer .com .com .com .com 4 .com u datasheet
286 chapter 10 8-/16-bit ppg timer 10.1 overview of 8-/16-bit ppg timer the 8-/16-bit ppg timer is a reload timer module with two channels (ppg0 and ppg1) that outputs a pulse in any cycle and at any duty ratio. a combination of two channels provides: 8-bit ppg output 2-channel independent operation mode 16-bit ppg output operation mode 8 + 8-bit ppg out put operation mode the mb90385 series has two 8-/16-bit ppg timers . this section expl ains the functions of ppg0/1. ppg2/3 has t he same functions as ppg0/1. functions of 8-/16-bit ppg timer the 8-/16-bit ppg timer consists of four 8-bit reload registers (prlh0, prll0, prlh1, and prll1) and two ppg down counters (pcnt0 and pcnt1). individual setting of high and low widths in output pulse enables an output pulse of any cycle and duty ratio. the count clock can be select ed from six internal clocks. the 8-/16-bit ppg timer can be us ed as an interval timer by gene rating an interrupt request at each interval time. an external circuit enables the 8-/16-bit ppg timer to be used as a d/a converter. operation modes of 8-/16-bit ppg timer 8-bit ppg output 2-channel independent operation mode the 8-bit ppg output 2-channel independent operat ion mode causes the 2-ch annel modules (ppg0 and ppg1) to operate as each in dependent 8-bit ppg timer. table 10.1-1 shows the interval times in the 8-bit ppg output 2-channel independent operation mode. .com .com .com .com 4 .com u datasheet
287 chapter 10 8-/16-bit ppg timer 16-bit ppg output operation mode the 16-bit ppg output operation mode concatenates the 2-channel modules (ppg0 and ppg1) to operate as a 16-bit 1-channel ppg timer. table 10.1-2 shows the interval times in this mode. table 10.1-1 interval times in 8-bit ppg output 2-channel independent operation mode count clock cycle ppg0, ppg1 interval time output pulse time 1/ (62.5 ns) 1/ to 2 8 / 2/ to 2 9 / 2/ (125 ns) 2/ to 2 9 / 2 2 / to 2 10 / 2 2 / (250 ns) 2 2 / to 2 10 / 2 3 / to 2 11 / 2 3 / (500 ns) 2 3 / to 2 11 / 2 4 / to 2 12 / 2 4 / (1 s) 2 4 / to 2 12 / 2 5 / to 2 13 / 2 9 /hclk (128 s) 2 9 /hclk to 2 17 /hclk 2 10 /hclk to 2 18 /hclk hclk: oscillation clock : machine clock frequency the parenthesized values are provided when the os cillation clock operates at 4 mhz and the machine clock operates at 16 mhz. table 10.1-2 interval times in 16-bit ppg output operation mode count clock cycle interval time output pulse time 1/ (62.5 ns) 1/ to 2 16 / 2/ to 2 17 / 2/ (125 ns) 2/ to 2 17 / 2 2 / to 2 18 / 2 2 / (250 ns) 2 2 / to 2 18 / 2 3 / to 2 19 / 2 3 / (500 ns) 2 3 / to 2 19 / 2 4 / to 2 20 / 2 4 / (1 s) 2 4 / to 2 20 / 2 5 / to 2 21 / 2 9 /hclk (128 s) 2 9 /hclk to 2 25 /hclk 2 10 /hclk to 2 26 /hclk hclk: oscillation clock : machine clock frequency the parenthesized values are provided when the os cillation clock operates at 4 mhz and the machine clock operates at 16 mhz. .com .com .com .com 4 .com u datasheet
288 chapter 10 8-/16-bit ppg timer 8 + 8-bit ppg output operation mode the 8 + 8-bit ppg output operation mode causes the ppg0 of the 2-channel modules (ppg0 and ppg1) to operate as an 8-bit prescaler and th e underflow output of the ppg0 to operate as the count clock of the ppg1. table 10.1-3 shows the interval times in this mode. table 10.1-3 interval times in 8+8-bit ppg output operation mode count clock cycle ppg0 ppg1 interval time output pulse time interval time output pulse time 1/ (62.5 ns) 1/ to 2 8 / 2/ to 2 9 / 1/ to 2 16 / 2/ to 2 17 / 2/ (125 ns) 2/ to 2 9 / 2 2 / to 2 10 / 2/ to 2 17 / 2 2 / to 2 18 / 2 2 / (250 ns) 2 2 / to 2 10 / 2 3 / to 2 11 / 2 2 / to 2 18 / 2 3 / to 2 19 / 2 3 / (500 ns) 2 3 / to 2 11 / 2 4 / to 2 12 / 2 3 / to 2 19 / 2 4 / to 2 20 / 2 4 / (1 s) 2 4 / to 2 12 / 2 5 / to 2 13 / 2 4 / to 2 20 / 2 5 / to 2 21 / 2 9 /hclk (128 s) 2 9 /hclk to 2 17 /hclk 2 10 /hclk to 2 18 /hclk 2 9 /hclk to 2 25 /hclk 2 10 /hclk to 2 26 /hclk hclk: oscillation clock : machine clock frequency the parenthesized values are provided when the os cillation clock operates at 4 mhz and the machine clock operates at 16 mhz. .com .com .com .com 4 .com u datasheet
289 chapter 10 8-/16-bit ppg timer 10.2 block diagram of 8-/16-bit ppg timer the mb90385 series contai ns two 8/16-bit ppg timer (each with two channels). one 8-/16-bit ppg timer consists of 8-bit ppg ti mers with two channels. this section shows the block diagrams for the 8-/16-bit ppg time r 0 and 8-/16-bit ppg timer 1. the ppg2 has the same function as the ppg0, and ppg3 has the same function as ppg1. channels and ppg pi ns of ppg timers figure 10.2-1 shows the relationship between the channe ls and the ppg pins of the 8-/16-bit ppg timers in the mb90385 series. figure 10.2-1 channels and ppg pins of ppg timers ppg0/1 pin ppg0 output pin pin ppg1 output pin ppg2/3 pin ppg2 output pin pin ppg3 output pin .com .com .com .com 4 .com u datasheet
290 chapter 10 8-/16-bit ppg timer 10.2.1 block diagram for 8-/16-bit ppg timer 0 the 8-/16-bit ppg tim er 0 consists of the following blocks. block diagram of 8-/16-bit ppg timer 0 figure 10.2-2 block diagra m of 8-/16-bit ppg timer 0 ppg0 down counter (pcnt0) reload register l/h selector ppg0 temporary buffer 0 (prlbh0) low level side data bus high level side data bus ppg0 operation mode control register (ppgc0) ppg0/1 count clock select register (ppg01) ppg0 output latch timebase timer output (512/hclk) resource clock (1/ ) resource clock (2/ ) resource clock (4/ ) resource clock (8/ ) resource clock (16/ ) pin ppg0 interrupt request output* reload select signal count start value invert ppg output control circuit clear pulse selector operation mode control signal ppg0 reload register underflow clk select signal ppg1 underflow ppg0 underflow (to ppg1) r sq count clock selector pen0 pe0 pie0 puf0 ?? reserved ? pcs2 pcs0 pcm2 pcm1 pcm0 ?? pcs1 3 2 ? : unused reserved : reserved bit hclk : oscillation clock frequency : machine clock frequency * : the interrupt output of 8-/16- bit ppg timer 0 is combined to one interrupt by or circuit with the interrupt request output of ppg timer 1. prlh0 (high level side) prll0 (low level side) .com .com .com .com 4 .com u datasheet
291 chapter 10 8-/16-bit ppg timer details of pins in block diagram table 10.2-1 lists the actual pin names and interr upt request numbers of the 8-/16-bit ppg timer. ppg operation mode control register 0 (ppgc0) this register enables or disables operation of the 8-/16-bit ppg timer 0, the pin output, and an underflow interrupt. it also i ndicates the occurrence of an underflow. ppg0/1 count clock select register (ppg01) this register sets the count clock of the 8-/16-bit ppg timer 0. ppg0 reload registers (prlh0 and prll0) these registers set the high width or low width of the output pulse. the values set in these registers are reloaded to the ppg0 down counter (pcnt0) when the 8-/16-bit ppg timer 0 is started. ppg0 down counter (pcnt0) this counter is an 8-bit down counter that alternatel y reloads the values set in the ppg0 reload registers (prlh0 and prll0) to decrement. wh en an underflow occurs, the pin output is inverted. this counter is concatenated for use as a singl e-channel 16-bit ppg down counter. ppg0 temporary buffer (prlbh0) this buffer prevents deviation of the output puls e width caused at writing to the ppg reload registers (prlh0 and prll0). this buffer stores the prlh0 va lue temporarily and enables it in synchronization with the timing of writing to the prll0. reload register l/h selector this selector detects the current pin output level to select whic h register value, low reload register (prll0) or high reload register (prlh0), should be reloaded to the ppg0 down counter. count clock selector this selector selects the count clock to be input to the ppg0 down counter from five frequency-divided clocks of the machine clock or the freque ncy-divided clocks of the timebase timer. table 10.2-1 pins and interrupt request numbers in block diagram channel output pin interrupt request number ppg0 p14/ppg0 #22 (16 h ) ppg1 p15/ppg1 ppg2 p16/ppg2 #26 (1a h ) ppg3 p17/ppg3 .com .com .com .com 4 .com u datasheet
292 chapter 10 8-/16-bit ppg timer ppg output control circuit this circuit inverts the pin output level and the output when an underflow occurs. .com .com .com .com 4 .com u datasheet
293 chapter 10 8-/16-bit ppg timer 10.2.2 block diagram of 8-/16-bit ppg timer 1 the 8-/16-bit ppg tim er 1 consists of the following blocks. block diagram of 8-/16-bit ppg timer 1 figure 10.2-3 block diagra m of 8-/16-bit ppg timer 1 ppg1 down counter (pcnt1) reload register l/h selector ppg1 temporary buffer (prlbh1) high level side data bus low level side data bus ppg1 operation mode control register ( ppgc1) ppg1 output latch pin interrupt request output* reload select signal count start value invert ppg output control circuit clear ppg1 reload register underflow clk md0 select signal ppg0 underflow (from ppg0) operation mode control signal ppg1 underflow (to ppg0) r s q count clock selector pen1 pe1 pie1 puf1 md1 md0 reserved ? ppg0/1 count clock select register (ppg01) timebase timer output (512/hclk) resource clock (1/ ) resource clock (2/ ) resource clock (4/ ) resource clock (8/ ) resource clock (16/ ) pcs2 pcs0 pcm2 pcm1 pcm0 ?? pcs1 3 2 prlh1 (high side) prll1 (low side) ppg1 ? : unused reservation : reserved bit hclk : oscillation clock frequency : machine clock frequency * : the interrupt output of 8-/16- bit ppg timer 1 is combined to one interrupt by or circuit with the interrupt request output of ppg timer 0. .com .com .com .com 4 .com u datasheet
294 chapter 10 8-/16-bit ppg timer details of pins in block diagram table 10.2-2 lists the actual pin names and interr upt request numbers of the 8-/16-bit ppg timer. ppg operation mode control register 1 (ppgc1) this register sets the operation mode of the 8-/16-bit ppg timer, enables or disables the operation of the 8-/ 16-bit ppg timer 1, the pin output and an underflow in terrupt, and also indicates the generation of an underflow. ppg2/3 count clock select register (ppg23) this register sets the count clock of the 8-/16-bit ppg timer 1. ppg1 reload registers (prlh1 and prll1) these registers set the high width or low width of the output pulse. the values set in these registers are reloaded to the ppg1 down counter (pcnt1) when the 8-/16-bit ppg timer 1 is started. ppg1 down counter (pcnt1) this counter is an 8-bit down counter that alternatel y reloads the values set in the ppg1 reload registers (prlh1 and prll1) to decrement. when an underflo w occurs, the pin output is inverted. the 2-channel ppg down counters (ppg0 and ppg1) can also be conn ected for use as a singl e-channel 16-bit ppg down counter. ppg1 temporary buffer (prlbh1) this buffer prevents deviation of the output puls e width caused at writing to the ppg reload registers (prlh1 and prll1). it stores the prlh1 value tem porarily and enables it in synchronization with the timing of writing to the prll1. reload register l/h selector this selector detects the current pin output level to select whic h register value, low reload register (prll1) or high reload register (prlh1), should be reloaded to the ppg1 down counter. count clock selector this selector selects the count clock to be input to the ppg1 down counter from five frequency-divided clocks of the machine clock or the freque ncy-divided clocks of the timebase timer. table 10.2-2 pins and interrupt request numbers in block diagram channel output pin interrupt request number ppg0 p14/ppg0 #22 (16 h ) ppg1 p15/ppg1 ppg2 p16/ppg2 #26 (1a h ) ppg3 p17/ppg3 .com .com .com .com 4 .com u datasheet
295 chapter 10 8-/16-bit ppg timer ppg output control circuit this circuit inverts the pin output level and the output when an underflow occurs. .com .com .com .com 4 .com u datasheet
296 chapter 10 8-/16-bit ppg timer 10.3 configuration of 8-/16-bit ppg timer this section explains t he pins, registers and interrupt fact ors of the 8-/ 16-bit ppg timer. pins of 8-/16-bit ppg timer the pins of the 8-/16-bit ppg timer serve as genera l-purpose i/o ports. table 10.3-1 indicates the pin functions and pin settings required to use the 8-/16-bit ppg timer. block diagram of 8-/ 16-bit ppg timer pins see "chapter 4 i/o port" for the pin block diagram. table 10.3-1 pins of 8-/16-bit ppg timer channel pin name pin function pin setting required for use of 8- /16-bit ppg timer ppg0 ppg0 output pin general-purpose i/o port, ppg0 output pin set ppg0 pin output to "enabled" (ppgc0: pe=1) ppg1 ppg1 output pin general-purpose i/o port, ppg1 output pin set ppg1 pin output to "enabled" (ppgc1: pe1=1) ppg2 ppg2 output pin general-purpose i/o port, ppg2 output pin set ppg2 pin output to "enabled" (ppgc2: pe0=1) ppg3 ppg3 output pin general-purpose i/o port, ppg3 output pin set ppg3 pin output to "enabled" (ppgc3: pe1=1) .com .com .com .com 4 .com u datasheet
297 chapter 10 8-/16-bit ppg timer list of registers and reset va lues of 8-/16-bit ppg timer figure 10.3-1 list of registers and reset values of 8-/16-bit ppg timer generation of interrupt request from 8-/16-bit ppg timer in the 8-/16-bit ppg timer, the underflow generation fl ag bits in the ppg operation mode control registers (ppgc0: puf0, ppgc1: puf1) are set to 1 when an underflow occurs. if the underflow interrupts of channels causing an underflo w are enabled (ppgc0: pie0 = 1, ppgc1: pie1 = 1), an underflow interrupt request is generated to the interrupt controller. x: undefined bit151413121110 9 8 ppg0 operation mode control register: h (ppgc1) 00000000 bit76543210 ppg0 operation mode control register : l (ppgc0) 00000000 bit76543210 ppg0/1 count clock select register (ppg01) 00000000 bit151413121110 9 8 ppg0 reload register: h (prlh0) xxxxxxxx bit76543210 ppg0 reload register: l (prll0) xxxxxxxx bit151413121110 9 8 ppg1 reload register: h (prlh1) xxxxxxxx bit76543210 ppg1 reload register: l (prll1) xxxxxxxx .com .com .com .com 4 .com u datasheet
298 chapter 10 8-/16-bit ppg timer 10.3.1 ppg0 operation mode control register (ppgc0) the ppg0 operation mode control register (ppgc0) provi des the following settings: enabling or disabling operati on of 8-/16-bit ppg timer switching between pin functions (e nabling or disabling pulse output) enabling or disabling underflow interrupt setting underflow in terrupt request flag ppg0 operation mode cont rol register (ppgc0) figure 10.3-2 ppg0 operation mode control register (ppgc0) 0x000xx1 b 4 5321 7 6 0 puf0 bit 3 0 1 pie0 bit 4 0 1 pe0 bit 5 0 1 pen0 bit 7 0 1 ? ? r/w r/w r/w ? w r/w 1 bit 0 r/w : read/write x : undefined ? : unused : reset value reset value reserved reserved bit underflow generation flag bit underflow interrupt enable bit always set to "1" no underflow underflow interrupt request disable interrupt request enable ppg0 pin output enable bit general-purpose i/o port (pulse output disable) ppg0 output (pulse output enable) ppg0 operation enable bit couting disable (holds "l" level output) counting enable clears puf0 bit no effect read write .com .com .com .com 4 .com u datasheet
299 chapter 10 8-/16-bit ppg timer table 10.3-2 functions of ppg0 operation mode control register (ppgc0) bit name function bit 0 reserved: reserved bit always set this bit to 1. bit 1 bit 2 unused bits read: the value is undefined. write: no effect bit 3 puf0: underflow generation flag bit 8-bit ppg output 2-channel independent operation mode, 8+8-bit ppg output operation mode: when the value of the ppg0 down counter is decremented from "00 h " to "ff h ", an underflow occurs (puf0 = 1). 16-bit ppg output operation mode: when the values of the ppg0 and ppg1 down counters are decremented from "0000 h " to" ffff h ", an underflow occurs (puf0 = 1). when an underflow occurs (puf0 = 1) with an underflow interrupt enabled (pie0 = 1), an interrupt request is generated. when set to 0: clears this bit when set to 1: no effect read by read modify write instructions: 1 read bit 4 pie0: underflow interrupt enable bit this bit enables or disables an interrupt. when set to 0: no interrupt request generated even at underflow (puf0 = 1). when set to 1: interrupt request generated at underflow (puf0 = 1) bit 5 pe0: ppg0 pin output enable bit this bit switches between ppg0 pin func tions and enables or disables the pulse output. when set to 0: ppg0 pin functions as general-purpose i/o port. the pulse output is disabled. when set to 1: ppg0 pin functions as ppg0 output pin. the pulse output is enabled. bit 6 unused bit read: the value is undefined. write: no effect bit 7 pen0: ppg0 operation enable bit this bit enables or disables the count operation of the 8-/16-bit ppg timer 0. when set to 0: count operation disabled when set to 1: count operation enabled when the count operation is disabled (p en0 = 0), the output is held at a low level. .com .com .com .com 4 .com u datasheet
300 chapter 10 8-/16-bit ppg timer 10.3.2 ppg1 operation mode control register (ppgc1) the ppg1 operation mode control register (ppgc1) provi des the following settings: enabling or disabling operati on of 8-/16-bit ppg timer switching between pin functions (e nabling or disabling pulse output) enabling or disabling underflow interrupt setting underflow in terrupt request flag setting the operation mode of the 8-/16-bit ppg timer ppg1 operation mode cont rol register (ppgc1) figure 10.3-3 ppg1 operation mode control register (ppgc1) 0x000001 b puf1 bit 11 0 1 pie1 bit 12 0 1 pe1 bit 13 0 1 pen1 bit 15 0 1 md1 bit 10 0 0 1 1 md0 bit 9 0 1 0 1 r/w r/w r/w r/w r/w ? w r/w 12 13 11 10 9 14 8 15 1 bit 8 r/w : read/write x : undefined ? : unused : reset value reset value reserved reserved bit always set to "1" operation mode select bits underflow generation flag bit underflow interrupt enable bit 8-bit ppg output 2-ch independent operation mode 8 + 8-bit ppg output operation mode setting disable 16-bit ppg output operation mode read write no underflow underflow underflow interrupt request disable underflow interrupt request enable ppg1 pin output enable bit general-purpose i/o port (pulse output disable) ppg1 output (pulse output enable) ppg1 operation enable bit counting disable (holds "l" level output) counting enable clears puf1 bit no effect .com .com .com .com 4 .com u datasheet
301 chapter 10 8-/16-bit ppg timer table 10.3-3 functions of ppg1 operation mode control register (ppgc1) bit name function bit 8 reserved: reserved bit always set this bit to 1. bit 9 bit 10 md1, md0: operation mode select bits these bits set the operation mode of the 8-/16-bit ppg timer. [any mode other than 8-bit ppg outp ut 2-channel inde pendent operation mode] use a word instruction to set the ppg operation enable bits (pen0 and pen1) at one time. do not set operation of only one of the two channels (pen1 = 0/pen0 = 1 or pen1 = 1/pen0 = 0). note: do not set the md1 and md0 bits to "10 b ". bit 11 puf1: underflow generation flag bit 8-bit ppg output 2-channel independent operation mode, 8+8-bit ppg output operation mode: when the value of the ppg1 down counter is decremented from "00 h " to "ff h ", an underflow occurs (puf1 = 1). 16-bit ppg output operation mode: when the values of the ppg0 and ppg1 down counters are decremented from "0000 h " to "ffff h ", an underflow occurs (puf1 = 1). when an underflow occurs (puf1 = 1) with an underflow interrupt enabled (pie1 = 1), an interrupt request is generated. when set to 0: clears this bit when set to 1: no effect read by read modify write instructions: 1 is read. bit 12 pie1: underflow interrupt enable bit this bit enables or disables an interrupt. when set to 0: no interrupt request is generated even at underflow (puf1 = 1) when set to 1: interrupt request is generated at underflow (puf1 = 1) bit 13 pe1: ppg1 pin output enable bit this bit switches between ppg1 pin func tions and enables or disables the pulse output. when set to 0: ppg1 pin functions as genera l-purpose i/o port. the pulse output is disabled. when set to 1: ppg1 pin functions as ppg1 output pin. the pulse output is enabled. bit 14 unused bit read: the value is undefined. write: no effect bit 15 pen1: ppg1 operation enable bit this bit enables or disables the count operation of the 8-/16-bit ppg timer 1. when set to 0: count operation disabled when set to 1: count operation enabled when the count operation is disabled (p en1 = 0), the output is held at a low level. .com .com .com .com 4 .com u datasheet
302 chapter 10 8-/16-bit ppg timer 10.3.3 ppg0/1 count clock select register (ppg01) the ppg0/1 count clock select r egister (ppg01) sel ects the count clock of the 8-/16-bit ppg timer. ppg0/1 count clock se lect register (ppg01) figure 10.3-4 ppg0/1 count clock select register (ppg01) 000000xx b 4 53210 7 6 pcm2 1/ (62.5 ns) 2/ (125 ns) 2 2 / (250 ns) 2 3 / (500 ns) 2 4 / (1 s) setting disable setting disable 2 9 /hclk (128 s) bit 4 bit 3 bit 2 0 0 0 0 1 1 1 1 pcm1 0 0 1 1 0 0 1 1 pcm0 0 1 0 1 0 1 0 1 pcs2 1/ (62.5 ns) 2/ (125ns) 2 2 / (250 ns) 2 3 / (500 ns) 2 4 / (1 s) setting disable setting disable 2 9 /hclk (128 s) bit 7 bit 6 bit 5 0 0 0 0 1 1 1 1 pcs1 0 0 1 1 0 0 1 1 pcs0 0 1 0 1 0 1 0 1 ? r/w r/w r/w r/w r/w ? r/w r/w : read/write x : undefined ? : unused : reset value hclk : oscillation clock : machine clock frequency the parenthesized values are provided when the oscillation clock operates at 4 mhz and the machine clock operates at 16 mhz. ppg0 count clock select bits ppg1 count clock select bits reset value .com .com .com .com 4 .com u datasheet
303 chapter 10 8-/16-bit ppg timer table 10.3-4 functions of ppg0/1 count clock select register (ppg01) bit name function bit 0 bit 1 unused bits read: the value is undefined. write: no effect bit 2 to bit 4 pcm2 to pcm0: ppg0 count clock select bit these bits set the count clock of the 8-/16-bit ppg timer 0. the count clock can be selected from five frequency-divided clocks of the machine clock and the frequency-divided clocks of the timebase timer. bit 5 to bit 7 pcs2 to pcs0: ppg1 count clock select bits these bits set the count clock of the 8-/16-bit ppg timer 1. the count clock can be selected from five frequency-divided clocks of the machine clock and the frequency-divided clocks of the timebase timer. the settings of the ppg1 count clock select bits (pcs2 to pcs0) are enabled only in the 8-bit ppg output 2-channel independent mode (ppgc1: md1, md0 = "00 b "). .com .com .com .com 4 .com u datasheet
304 chapter 10 8-/16-bit ppg timer 10.3.4 ppg reload registers (prll0/prlh0, prll1/prlh1) the value (reload value) from which the ppg down counter st arts counting is set in the ppg reload registers, which ar e an 8-bit register at low le vel and an 8-bit register at high level. ppg reload registers ( prll0/prlh0, prll1/prlh1) figure 10.3-5 ppg reload registers (prll0/prlh0, prll1/prlh1) table 10.3-5 indicates the functions of the ppg reload registers. r/w: read/write x: undefined bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 reset value prlh0/prlh1 d15 d14 d13 d12 d11 d10 d9 d8 xxxxxxxx b r/w r/w r/w r/w r/w r/w r/w r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset value prll0/prll1 d7 d6 d5 d4 d3 d2 d1 d0 xxxxxxxx b r/w r/w r/w r/w r/w r/w r/w r/w table 10.3-5 functions of ppg reload registers function 8-/16-bit ppg timer 0 8-/16-bit ppg timer 1 retains reload value on low-level side prll0 prll1 retains reload value on high-level side prlh0 prlh1 notes: in the 16-bit ppg output operation mode (ppgc1: md1, md0 = "11 b "), use a long-word instruction to set the ppg reload registers or the word instruction to set the ppg0 and ppg1 in this order. in the 8 + 8-bit ppg output operation mode (ppgc1: md1, md0 = "01 b "), set the same value in both the low-level and high-level ppg reload registers (prtll0/prlh0) of the 8-/16-bit ppg timer 0. setting a different value in the low-level and high-level ppg reload registers may cause the 8-/16-bit ppg timer 1 to have different ppg output waveforms at each clock cycle. .com .com .com .com 4 .com u datasheet
305 chapter 10 8-/16-bit ppg timer 10.4 interrupts of 8-/16-bit ppg timer the 8-/16-bit ppg timer can g enerate an interrupt request when the ppg down counter underflows. it corresponds to the ei 2 os. interrupts of 8-/ 16-bit ppg timer table 10.4-1 shows the interrupt control bits an d interrupt factor of the 8-/16-bit ppg timer. [8-bit ppg output 2-channel independent operation mode or 8 + 8-bit ppg output operation mode] in the 8-bit ppg output 2-channel independent operation mode or the 8 + 8-bit ppg output operation mode, the ppg0 and ppg1 timers can generate an interrupt independently. when the value of the ppg0 or ppg1 down counter is decremented from "00 h " to "ff h ", an underflow occurs. when an underflow occurs, the underflow generation flag bit in the channel causing an underflow is set (ppgc0: puf0 = 1 or ppgc1: puf1 = 1). if an interrupt request from th e channel that causes an underflow is enabled (ppgc0: pie0 = 1 or ppgc1: pie1 = 1), an interrupt request is generated. [16-bit ppg output operation mode] in the 16-bit ppg output operation mode, when the values of the ppg0 and ppg1 down counters are decremented from "0000 h " to "ffff h ", an underflow occurs. when an underflow occurs, the underflow generation flag bits in the two channels are set at one time (ppgc0: puf0 = 1 and ppgc1: puf1 = 1). when an underflow occurs with either of the tw o channel of the interrupt requests enabled (ppgc0: pie1 = 0, ppgc1: pie1 = 1 or ppgc0: pie1 = 1, pp gc1: pie1 = 0), an interrupt request is generated. to prevent duplication of interrupt requests, disable either of the two channel of the underflow interrupt enable bits (ppgc0: pie1 = 0, ppgc1: pie1 = 1 or ppgc0: pie1 = 1, ppgc1: pie1 = 0). when the two channels of the underflow generation flag bits are set (ppgc0: puf0 = 1 and ppgc1: puf1 = 1), clear the two channels at the same time. correspondence between 8-/16-bit ppg timer inte rrupt and ei 2 os for details of the interrupt number, interrupt contro l register, and interrupt vector address, see "3.5 interrupt". table 10.4-1 interrupt control bits of 8-/16-bit ppg timer ppg0 ppg1 interrupt request flag bit pppgc0: puf0 ppgc1: puf1 interrupt request enable bit ppgc0: pie0 ppgc1: pie1 interrupt factor underflow in ppg0 down counter underflow in ppg1 down counter .com .com .com .com 4 .com u datasheet
306 chapter 10 8-/16-bit ppg timer 8-/16-bit ppg timer interrupt and ei 2 os function the 8-/16-bit ppg timer corresponds to the ei 2 os function. generation of an enabled interrupt factor starts the ei 2 os. however, it is necessary to disable generatio n of interrupt requests by resources sharing the interrupt control register (icr) with the 8-/16-bit ppg timer. .com .com .com .com 4 .com u datasheet
307 chapter 10 8-/16-bit ppg timer 10.5 explanation of operation of 8-/16-bit ppg timer the 8-/16-bit ppg timer output s a pulse width at any frequenc y and at any duty ratio continuously. operation of 8-/16-bit ppg timer output operation of 8-/16-bit ppg timer the 8-/16-bit ppg timer has two (low-level and hi gh-level) 8-bit reload registers (prll0/prlh0 and prll1/prlh1) for each channel. the values set in the 8-bit reload registers (prl l0/prlh0 and prll1/prlh1) are reloaded alternately to the ppg down counters (pcnt0 and pcnt1). after reloading the values in the ppg down count ers, decrementing is perf ormed in synchronization with the count clocks set by the ppg count clock select bits (ppg01: pcm2 to pcm0 and pcs1 and pcs0). if the values set in the reload registers are relo aded to the ppg down counters when an underflow occurs, the pin output is inverted. figure 10.5-1 shows the output waveform of the 8-/16-bit ppg timer. figure 10.5-1 output waveform of 8-/16-bit ppg timer operation modes of 8-/16-bit ppg timer as long as the operation of the 8-/16-bit ppg timer is enabled (ppgc0: pen0 = 1, ppgc1: pen1 = 1), a pulse waveform is output continuously from the ppg ou tput pin. a pulse width of any frequency and duty ratio can be set. the pulse output of the 8-/16-bit ppg timer is not stopped until operation of the 8-/16-bit ppg timer is stopped (ppgc0: pen0 = 0, ppgc1: pen1 = 0). 8-bit ppg output 2-channel independent operation mode 16-bit ppg output operation mode 8 + 8-bit ppg output operation mode t (l + 1) t (h + 1) operation start operation stop ppg operation enable bit (pen) ppg output pin l : value of ppg reload register (prll) h : value of ppg reload register (prlh) t : count clock cycle .com .com .com .com 4 .com u datasheet
308 chapter 10 8-/16-bit ppg timer 10.5.1 8-bit ppg output 2-channel independent operation mode in the 8-bit ppg output 2- channel independent operation mode , the 8-/16-bit ppg timer is set as an 8-bit ppg timer with two independent channels. ppg output operation and interrupt request generation can be per formed independently for each channel. setting for 8-bit ppg output 2- channel independent operation mode operating the 8-/16-bit ppg timer in the 8-bit ppg output 2-channel independent operation mode requires the setting shown in figure 10.5-2. figure 10.5-2 setting for 8-bit ppg output 2-channel independent operation mode note: use the word instruction to set both high-level and low-level ppg reload registers (prll0/prlh0 and prll1/prlh1) at the same time. : used bit ? : unused bit 1: set 1 0: set 0 bit1514131211109bit8bit7654321bit0 ppgc1/ppgc0 pen1 ? pe1 pie1 puf1 md1 md0 reser ved pen0 ? pe0 pie0 puf0 ?? reser ved 1 0011 1 ppg01 (reserved area) pcs2 pcs1 pcs0 pcm 2 pcm 1 pcm 0 ?? prlh0/prll0 ppg0 set high level side reload values. ppg0 set low level side reload values. prlh1/prll1 ppg1 set high level side reload values. ppg1 set low level side reload values. .com .com .com .com 4 .com u datasheet
309 chapter 10 8-/16-bit ppg timer operation in 8-bit ppg output 2-channel independent operation mode the 8-bit ppg timer with two channels performs an independent ppg operation. when the pin output is enabled (ppgc0: pe0 = 1, ppgc1: pe1 = 1), the ppg0 pulse wave is output from the ppg0 pin and the ppg1 pulse wave is output from the ppg1 pin. when the reload value is set in the ppg reload registers (prll0/prlh0 a nd prll1/prlh1) to enable the operation of the ppg timer ( ppgc0: pen0 = 1, ppgc1: pen1 = 1), the ppg down counter of the enabled channel starts counting. to stop the count operation of the ppg down counter, disable the operation of the ppg timer of the channel to be stopped (ppgc0: pen0 = 0, ppgc1: pen1 = 0). the count operation of the ppg down counter is stopped and the output of the ppg output pin is held at a low level. when the ppg down counter of each channel underf lows, the reload values set in the ppg reload registers (prll0/prlh0 and prll1 /prlh1) are reloaded to the ppg down counter that underflows. when an underflow occurs, the underflow generation flag bit in the channel that causes an underflow is set (ppgc0: puf0 = 1, ppgc1: puf1 = 1). if an interrupt request is enabled at the channel that causes an underflow (ppgc0: pie0 = 1, ppgc1: pie1 = 1), the interrupt request is generated. output waveform in 8-bit ppg output 2-channel independent operation mode the high and low pulse widths to be output are determined by adding 1 to the value in the ppg reload register and multiplying it by the count clock cycle. for example, if the value in the ppg reload register is "00 h ", the pulse width has one count clock cycle, and if the value is "ff h ", the pulse width has 256 count clock cycles. the equations for calculating the pulse width are shown below: p l = t x (l + 1) p h = t x (h + 1) p l : low width of output pulse p h : high width of output pulse l: values of 8 bits in ppg reload register (prll0 or prll1) h: values of 8 bits in ppg reload register (prlh0 or prlh1) t: count clock cycle figure 10.5-3 shows the output waveform in the 8-bit ppg output 2-channel independent operation mode. figure 10.5-3 output waveform in 8-bit ppg output 2-channel independent operation mode t (l + 1) t (h + 1) operation start operation stop ppg operation enable bit (pen) ppg output pin l : value of ppg reload register (prll) h : value of ppg reload register (prlh) t : count clock cycle .com .com .com .com 4 .com u datasheet
310 chapter 10 8-/16-bit ppg timer 10.5.2 16-bit ppg output operation mode in the 16-bit ppg out put operation mode, the 8-/16-bit ppg timer is set as a 16-bit ppg timer with one channel. setting for 16-bit ppg ou tput operation mode operating the 8-/16-bit ppg timer in the 16-bit ppg output operation mode requires the setting shown in figure 10.5-4. figure 10.5-4 setting for 16-bit ppg output operation mode note: use a long-word instruction to set the values in the ppg reload registers or a word instruction to set the ppg0 and ppg1 (prll0 --> prll1 or prlh0 --> prlh1) in this order. : used bit x: undefined bit ? : unused bit 1: set 1 0: set 0 bit15 14 13 12 11 10 9 bit8 bit7 6 5 4 3 2 1 bit0 ppgc1/ppgc0 pen1 ? pe1 pie1 puf1 md1 md0 reser ved pen0 ? pe0 pie0 puf0 ?? reser ved 1 1111 1 ppg01 (reserved area) pcs2 pcs1 pcs0 pcm 2 pcm 1 pcm 0 ?? xxx prlh0/prll0 ppg0 set high level side reload values of lower 8 bits. ppg0 set low level side reload values of lower 8 bits. prlh1/prll1 ppg1 set high level side reload values of upper 8 bits. ppg1 set low level side reload values of upper 8 bits. .com .com .com .com 4 .com u datasheet
311 chapter 10 8-/16-bit ppg timer operation in 16-bit ppg output operation mode when either ppg0 pin output or ppg1 pin output is enabled (ppgc0: pe0 = 1, ppgc1: pe1 = 1), the same pulse wave is output from both the ppg0 and ppg1 pins. when the reload value is set in the ppg reload registers (prll0/prlh0 a nd prll1/prlh1) to enable operation of the ppg timer (ppgc0: pen0 = 1 and ppgc1: pen1 = 1) simultaneously, the ppg down counters start counting as 16-bit down counters (pcnt0 + pcnt1). to stop the count operation of the ppg down counte rs, disable the operation of the ppg timers of both channels (ppgc0: pen0 = 0 and ppgc1: pen1 = 0) simultaneously. the count operation of the ppg down counters is stopped and the output of the ppg output pin is held at a low level. if the ppg1 down counter underflows, the reload values set in the ppg0 and ppg1 reload registers (prll0/prlh0 and prll1/prlh1) are reloaded simultaneously to the ppg down counters (pcnt0 + pcnt1). when an underflow occurs, the underflow generation flag bits in both channe ls are set simultaneously (ppgc0: puf0 = 1, ppgc1: puf1 = 1). if an interr upt request is enabled at either channel (ppgc0: pie0 = 1, ppgc1: pie1 = 1), an interrupt request is generated. notes: in the 16-bit ppg output operation mode, the underflow generation flag bits in the two channels are set simultaneously when an underflow occurs (ppgc0: puf0 = 1 and ppgc1: puf1 = 1). to prevent duplication of interrupt requests, disable either of the underflow interrupt enable bits in the two channels (ppgc0: pie0 = 0, ppgc1: pie1 = 1 or ppgc0: pie0 = 1, ppgc1: pie1 = 0). if the underflow generation flag bits in the two channels are set (ppgc0: puf0 = 0 and ppgc1: puf1 = 0), clear the two channels at the same time. .com .com .com .com 4 .com u datasheet
312 chapter 10 8-/16-bit ppg timer output waveform in 16-bit ppg output operation mode the high and low pulse widths to be output are determined by adding 1 to the value in the ppg reload register and multiplying it by the count clock cycle. for example, if the value in the ppg reload register is "0000 h ", the pulse width has one count cloc k cycle, and if the value is "ffff h ", the pulse width has 65,536 count clock cycles. the equations for calculating the pulse width are shown below: pl= t x (l + 1) ph= t x (h + 1) pl: low width of output pulse ph: high width of output pulse l: values of 16 bits in ppg reload register (prll0 + prll1) h: values of 16 bits in ppg re load register (prlh0 + prlh1) t: count clock cycle figure 10.5-5 shows the output waveform in the 16-bit ppg output operation mode. figure 10.5-5 output waveform in 16-bit ppg output operation mode t (l + 1) t (h + 1) operation start operation stop ppg operation enable bit (pen) ppg output pin l : values of 16 bits in ppg reload register (prll1 + prll0) h : values of 16 bits in ppg reload register (prlh1 + prlh0) t : count clock cycle .com .com .com .com 4 .com u datasheet
313 chapter 10 8-/16-bit ppg timer 10.5.3 8+8-bit ppg output operation mode in the 8+8-bit ppg output operat ion mode, the 8-/16-bit ppg ti mer is set as an 8-bit ppg timer. the ppg0 operates as an 8-bit prescaler and the pp g1 operates using the ppg output of the ppg0 as a clock source. setting for 8+8-bit ppg output operation mode operating the 8-/16-bit ppg timer in the 8+8-bit pp g output operation mode requires the setting shown in figure 10.5-6. figure 10.5-6 setting for 8+8-bit ppg output operation mode note: use the word instruction to set both high-level and low-level ppg reload registers (prll0/prlh0 and prll1/prlh1) at the same time. : used bit x: undefined bit ? : unused bit 1: set 1 0: set 0 bit1514131211109bit8bit7654321bit0 ppgc1/ppgc0 pen1 ? pe1 pie1 puf1 md1 md0 reser ved pen0 ? pe0 pie0 puf0 ?? reser ved 1 0111 1 ppg01 (reserved area) pcs2 pcs1 pcs0 pcm 2 pcm 1 pcm 0 ?? xxx prlh0/prll0 ppg0 set high level side reload values. ppg0 set low level side reload values. prlh1/prll1 ppg1 set high level side reload values. ppg1 set low level side reload values. .com .com .com .com 4 .com u datasheet
314 chapter 10 8-/16-bit ppg timer operation in 8+8-bit ppg output operation mode the ppg0 operates as the prescaler of the ppg1 ti mer and the ppg1 operates using the ppg0 output as a count clock. when pin output is enabled (ppgc0: pe0 = 1, ppgc1 : pe1 = 1), the ppg0 pulse wave is output from the ppg0 pin and the ppg1 pulse wave is output form the ppg1 pin. when the reload value is set in the ppg reload registers (prll0/prlh0, prll1/prlh1) to enable operation of the ppg timer (ppgc0: pen0 = 1 and ppgc1: pen1 = 1), the ppg down counter starts counting. to stop the count operation of the ppg down counte rs, disable the operation of the ppg timers of both channels (ppgc0: pen0 = 0 and ppgc1: pen1 = 0) at the same time. the count operation of the ppg down counters is stopped and the output of the ppg output pin is held at a low level. if the ppg down counter of each channel underflows, the reload values set in the ppg reload registers (prll0/prlh0, prll1/prlh1) are reloaded to the ppg down counter that underflows. when an underflow occurs, the underflow generation flag bit in the channel that causes an underflow (ppgc0: puf0 = 1, ppgc1: puf1 = 1) is set. if an interrupt request is en abled at the channel that causes an underflow (ppgc0: pie0 = 1, ppgc1: pi e1 = 1), an interrupt request is generated. notes: do not operate ppg1 (ppgc1: pen1 = 1) when ppg0 is stopped (ppgc0: pen0 = 0). it is recommended to set the same value in both low-level and high-level ppg reload registers (prll0/prlh0, prll1/prlh1). .com .com .com .com 4 .com u datasheet
315 chapter 10 8-/16-bit ppg timer output waveform in 8+8-bit ppg output operation mode the high and low pulse widths to be output are determined by adding 1 to the value in the ppg reload register and multiplying it by the count clock cycle. the equations for calculating the pulse width are shown below: pl = t x (l 0 + 1) x (l 1 + 1) ph = t x (h 0 + 1) x (h 1 + 1) pl: low width of output pulse of ppg1 pin ph: high width of output pulse of ppg1 pin l 0 : values of 8 bits in ppg reload register (prll0) h 0 : values of 8 bits in ppg reload register (prlh0) l 1 : values of 8 bits in ppg reload register (prll1) h 1 : values of 8 bits in ppg reload register (prlh1) t: count clock cycle figure 10.5-7 shows the output waveform in the 8+8-bit ppg output operation mode. figure 10.5-7 output waveform in 8+8-bit ppg output operation mode t (l 0 + 1) (l 1 + 1) t (h 0 + 1) (h 1 + 1) operation start operation stop ppg operation enable bit (pen0, pen1) ppg1 output pin ppg0 output pin t (l 0 + 1) t (h 0 + 1) l 0 : values of 8 bits in ppg reload register (prll0) h 0 : values of 8 bits in ppg reload register (prlh0) h 1 : values of 8 bits in ppg reload register (prll1) l 1 : values of 8 bits in ppg reload register (prlh1) t : count clock cycle .com .com .com .com 4 .com u datasheet
316 chapter 10 8-/16-bit ppg timer 10.6 precautions when using 8-/16-bit ppg timer this section explains t he precautions when using t he 8-/16-bit ppg timer. precautions when using 8-/16-bit ppg timer effect on 8-/16-bit ppg timer when using timebase timer output if the output signal of the timebase timer is used as the input signal for the count clock of the 8-/16-bit ppg timer (ppg01: pcm2 to pcm0 = "111 b ", pcs2 to pcs0 = "111 b "), deviation may occur in the first count cycle in which the ppg timer is started by trigger input or in th e count cycle immediately after the ppg timer is stopped. when the timebase timer counter is cleared dur ing the count operation of the ppg down counter, deviation may occur in the count cycle. setting of ppg reload registers when using 8-bit ppg timer the low-level and high-level pulse widths are determin ed at the timing of relo ading the values in the low-level ppg reload registers (prll0 , prll1) to the ppg down counter. if the 8-bit ppg timer is used in the 8-bit ppg ou tput 2-channel independent operation mode or the 8 + 8-bit ppg output operation mode, use a word instruction to set both high-level and low-level ppg reload registers (prll0/prlh0, prll1/prlh1) at the same time. using a byte instruction may cause an unexpected pulse to be generated. [example of rewriting ppg reload registers using by te instruction] immediately before the signal level of the ppg pin sw itches from high to low, if the value in the high- level ppg reload register (prlh) is rewritten after the value in the low-level ppg reload register (prll) is rewritten using the byte instruction, a low-level pulse width is generated after rewriting and a high-level pulse width is generated before rewriting. figure 10.6-1 shows the waveform as the values in the ppg reload registers ar e rewritten using the byte instruction. figure 10.6-1 waveform when values in ppg reload registers rewritten using byte instruction ppg pin prlh prll aa a + b b bd ac bc b cdc d <1> <2> a + b c + d c + d c + d b + c timing of updating reload value <1>: change the value (a c) of ppg reload register (prll) <2>: change the value (b d) of ppg reload register (prlh) .com .com .com .com 4 .com u datasheet
317 chapter 10 8-/16-bit ppg timer setting of ppg reload registers when using 16-bit ppg timer use a long-word instruction to set the ppg reload registers (prll0/prlh0, prll1/prlh1) or a word instruction to set the ppg0 and ppg1 (prll0 --> prll1 or prlh0 --> prlh1) in this order. [reload timing in 16-bit ppg output operation mode] in the 16-bit ppg output operation mode, the reload va lues written to the ppg0 reload registers (prll0/ prlh0) are written temporarily to the temporary latch, written to the ppg1 reload registers (prll1/ prlh1), and then transferred to th e ppg0 reload registers (prll0/prl h0). therefore, when setting the reload value in the ppg1 reload registers (prll1/prl h1), it is necessary to set the reload value in the ppg0 reload registers (prll0/prlh0) simultaneously or set the reload value in the ppg0 reload registers (prll0/prlh0) before setting it in the ppg1 reload registers (prll1/prlh1). figure 10.6-2 shows the reload timing in the 16-bit ppg output operation mode. figure 10.6-2 reload timing in 16-bit ppg output operation mode ppg reload register (prll0, prlh0) ppg reload register (prll1, prlh1) temporary latch reload value of ppg0 reload value of ppg1 write to ppg0 except 16-bit ppg output operation mode only 16-bit ppg output operation mode transfers synchronously with writing to ppg1 write to ppg1 .com .com .com .com 4 .com u datasheet
318 chapter 10 8-/16-bit ppg timer .com .com .com .com 4 .com u datasheet
319 chapter 11 delayed interrupt generation module this chapter explains the f unctions and o perations of the delayed interrupt generation module. 11.1 overview of delayed interrupt generation module 11.2 block diagram of delayed interrupt generation module 11.3 configuration of delayed interrupt generation module 11.4 explanation of operation of delayed interrupt generation module 11.5 precautions when using delayed interrupt generation module 11.6 program example of delayed interrupt generation module .com .com .com .com 4 .com u datasheet
320 chapter 11 delayed interrupt generation module 11.1 overview of delayed interrupt generation module the delayed interrupt generati on module generates the inte rrupt for task switching. the hardware interrupt request can be generated/cancelled by software. overview of delayed in terrupt generation module by using the delayed interrupt generation module, a hardware interrupt request can be generated or cancelled by software. table 11.1-1 shows the overview of the delayed interrupt generation module. table 11.1-1 overview of delayed interrupt generate module function and control interrupt factor an interrupt request is generated by setting the r0 bit in the delayed interrupt request generate/cancel register to 1 (dirr: r0 = 1). an interrupt request is cancelled by setting the r0 bit in the delayed interrupt request generate/cancel register to 0 (dirr: r0 = 0). interrupt number #42 (2a h ) interrupt control an interrupt is not enabled by the dirr register. interrupt flag the interrupt flag is held in the r0 bit in the dirr register. ei 2 os the dirr register does not correspond to the ei 2 os. .com .com .com .com 4 .com u datasheet
321 chapter 11 delayed interrupt generation module 11.2 block diagram of delayed interrupt generation module the delayed interrupt gene ration module consists of the following blocks: interrupt request latch delayed interrupt request gener ate/cancel register (dirr) block diagram of delayed interrupt generation module figure 11.2-1 block diagram of delayed interrupt generation module interrupt request latch this latch keeps the settings (delayed interrupt reques t generation or cancellation) of the delayed interrupt request generate/cancel register (dirr). delayed interrupt request generate/cancel register (dirr) this register generates or cancels a delayed interrupt request. interrupt number the interrupt number used in the delayed interrupt generation module is as follows: interrupt number #42 (2a h ) delayed interrupt request generate/cancel register (dirr) ? : unused internal data bus s interrupt request r latch interrupt request signal ?????? ? r0 .com .com .com .com 4 .com u datasheet
322 chapter 11 delayed interrupt generation module 11.3 configuration of delayed interrupt generation module this section lists registers and reset values in the delay ed interrupt generation module. list of registers and r eset values in delayed in terrupt generation module figure 11.3-1 list of registers and reset values in delayed interrupt generation module x: undefined bit151413121110 9 8 delayed interrupt request generate/ cancel register (dirr) xxxxxxx0 .com .com .com .com 4 .com u datasheet
323 chapter 11 delayed interrupt generation module 11.3.1 delayed interrupt request generate/cancel register (dirr) the delayed interrupt request generate/cancel register (dirr) ge nerates or cancels a delayed interrupt request. delayed interrupt request gene rate/cancel register (dirr) figure 11.3-2 delayed interrupt request generate/cancel register (dirr) 0 1 r0 reset value xxxxxxx0 b 12 13 14 11 10 9 8 15 ? : unused r/w : read/write : reset value bit 8 r/w ? ? ? ? ? ? ? delayed interrupt request generate bit cancels delayed interrupt request generates delayed interrupt request table 11.3-1 functions of delayed interrupt request generate/cancel register (dirr) bit name function bit 8 r0: delayed interrupt request generate bit this bit generates or cancels a delayed interrupt request. when set to 0: cancels delayed interrupt request when set to 1: generates delayed interrupt request bit 9 to bit 15 unused bits read: the value is undefined write: no effect .com .com .com .com 4 .com u datasheet
324 chapter 11 delayed interrupt generation module 11.4 explanation of operation of delayed interrupt generation module the delayed interrupt generati on module has a function fo r generating or canceling an interrupt request by software. explanation of operati on of delayed interr upt generation module using the delayed interrupt generation module requires the setting shown in figure 11.4-1. figure 11.4-1 setting for delayed interrupt generation module when the r0 bit in the delayed interrupt request generate /cancel register (dirr) is set to 1 (dirr: r0 = 1), an interrupt request is generated. there is no interrupt request enable bit. operation of delayed interrupt generation module when the r0 bit in the delayed interrupt request genera te/cancel register (dirr) is set to 1, the interrupt request latch is set to 1 and an interrupt request is generated to the interrupt controller. when an interrupt request is preferred to other reques ts by the interrupt controller, the interrupt request is generated to the cpu. when the level of an interrupt request (icr: il) is pr eferred to that of the interrupt level mask bit (ilm) in the processor status (ps), the cpu delays inte rrupt processing until completion of execution of the current instruction. at interrupt processing, the user pr ogram sets the r0 bit to 0, cancels the interrupt request, and changes the task. figure 11.4-2 shows the operation of the delayed interrupt generation module. figure 11.4-2 operation of delayed interrupt generation module -: unused bit : :used bit bit151413121110 9bit8 pdirr -------r0 dirr icr yy icr xx delayed interrupt generation module cmp il ilm cmp other request interrupt controller cpu interrupt processing .com .com .com .com 4 .com u datasheet
325 chapter 11 delayed interrupt generation module 11.5 precautions when using delayed interrupt generation module this section explains the precautions when using the delayed interrupt generation module. precautions when using delayed interrupt generation module the interrupt processing is restarted at return from interrupt processing without setting the r0 bit in the delayed interrupt request generate/cancel register (dirr) to 0 within the interrupt processing routine. unlike software interrupts, interrupts in th e delayed interrupt generation module are delayed. .com .com .com .com 4 .com u datasheet
326 chapter 11 delayed interrupt generation module 11.6 program example of delayed interrupt generation module this section gives a program example of the delayed in terrupt generation module. program example of delayed interrupt generation module processing specifications the main program writes 1 to the r0 bit in the delayed interrupt request generate/cancel register (dirr), generates a delayed interrupt request, and changes the task. coding example icr15 equ 0000bfh ; interrupt control register dirr equ 00009fh ; delayed interrupt request generate/cancel register dirr_r0 equ dirr:0 ; delayed interrupt request generate bit ;-----main program--------------------------------------------------------------- code cseg start: ; stack pointer (sp) already initialized and ccr,#0bfh ; interrupt disabled mov i:icr15,#00h ; interrupt level 0 (highest) mov ilm,#07h ; ilm in ps set to level 7 or ccr, #40h ; interrupt enabled setb i:dirr_r0 ; delayed interrupt request generated loop mov a,#00h ; infinite loop mov a,#01h bra loop ;-----interrupt program---------------------------------------------------------- wari: clrb i:dirr_r0 ; interrupt request flag cleared : ; processing by user ; : reti ; return from interrupt code ends ;-----vector setting------------------------------------------------------------- vect cseg abs=0ffh org 00ff54h ; vector set to interrupt #42 (2ah) dsl wari org 0ffdch ; reset vector set dsl start db 00h ; set to single-chip mode vect ends end start .com .com .com .com 4 .com u datasheet
327 chapter 12 dtp/external interrupt this chapter explains the f unctions and o perations of dtp/external interrupt. 12.1 overview of dtp/external interrupt 12.2 block diagram of dtp/external interrupt 12.3 configuration of dtp/external interrupt 12.4 explanation of operation of dtp/external interrupt 12.5 precautions when using dtp/external interrupt 12.6 program example of dtp/external interrupt circuit .com .com .com .com 4 .com u datasheet
328 chapter 12 dtp/external interrupt 12.1 overview of dtp/external interrupt the dtp/external interrupt sends interrupt requests from exte rnal peripheral devices or data transfer requests to the cpu to generate an external interrupt request, or starts the ei 2 os. rx input of can controller can be used as exte rnal interrupt input. dtp/external interrupt function the interrupt request inputted to external interrupt input pins (int7 to int4) and rx input from external peripheral devices generates an external interrupt request, or starts the ei 2 os as an interrupt request from peripheral function. if the ei 2 os is disabled in the interrupt control register (icr: ise = 0), the external interrupt function is enabled, branching to interrupt processing. if the ei 2 os is enabled (icr: ise = 1), the dtp functio n is enabled and automatic data transfer is performed, branching to interrupt processing after the completion of data transfer for the specified number of times. table 12.1-1 shows an overview of the dtp/external interrupt. table 12.1-1 overview of dtp/external interrupt external interrupt dtp function input pin 5 pins (rx, int4 to int7) interrupt factor the interrupt factor is set in unit of pins using the detection level setting registers (elvr). input of high level, low level, rising edge, or falling edge input of high level or low level interrupt number #15 (0f h ), #24 (18 h ), #27 (1b h ) interrupt control the interrupt request output is enabled/disabled using the dtp/external interrupt enable register (enir). interrupt flag the interrupt factor is held using the dtp/external interrupt factor register (eirr) processing selection the ei 2 os is disabled. (icr: ise=0) the ei 2 os is enabled. (icr: ise=1) processing contents a branch is caused to the external interrupt processing. ei 2 os performs auto data transfer and completes the specified number of timer for data transfers, causing a branch to the interrupt processing. .com .com .com .com 4 .com u datasheet
329 chapter 12 dtp/external interrupt 12.2 block diagram of dtp/external interrupt the block diagram of the dtp/exte rnal interrupt is shown below. block diagram of dt p/external interrupt figure 12.2-1 block diagra m of dtp/external interrupt detection level setting register (elvr) dtp/external interrupt enable register (enir) dtp/external interrupt input detector la4 lb4 la5 lb5 la6 lb6 la7 lb7 la0 lb0 re- served re- served re- served re- served re- served re- served re- served re- served re- served re- served re- served re- served internal data bus en0 en4 en5 en6 en7 er0 er4 er5 er6 er7 dtp/external interrupt factor register (eirr) interrupt request signal interrupt request signal pin level edge selector level edge selector level edge selector level edge selector level edge selector pin pin pin pin int7 int6 int5 int4 rx .com .com .com .com 4 .com u datasheet
330 chapter 12 dtp/external interrupt dtp/external interrupt input detector this circuit detects interrupt requests or data transfer requests generated from external peripheral devices. the interrupt request flag bit corresponding to the pin w hose level or edge set by the detection level setting register (elvr) is detected is set to 1 (eirr: er). detection level setting register (elvr) this register sets the level or edge of input signals from external peripheral devices that cause dtp/external interrupt factors. dtp/external interrupt factor register (eirr) this register holds dtp/external interrupt factors. if an enable signal is input to the dtp/external in terrupt pin, the corresponding dtp/external interrupt request flag bit is set to 1. dtp/external interrupt enable register (enir) this register enables or disables dtp/external interrupt requests from external peripheral devices. details of pins and interrupt numbers table 12.2-1 shows the pins and interrupt num bers used in the dtp/external interrupt. table 12.2-1 pins and interrupt nu mbers used by dtp/external interrupt pin channel interrupt number p44/rx rx #15 (0f h ) p24/int4 4 #24 (18 h ) p25/int5 5 p26/int6 6 #27 (1b h ) p27/int7 7 .com .com .com .com 4 .com u datasheet
331 chapter 12 dtp/external interrupt 12.3 configuration of dtp/external interrupt this section lists and details the pins, interrupt fact ors, and registers in the dtp/ external interrupt. pins of dtp/external interrupt the pins used by the dtp/external interrupt serve as general-purpose i/0 ports. table 12.3-1 lists the pin functions and the pin sett ing required for use in the dtp/external interrupt block diagram of pins see "chapter 4 i/o port" for the block diagram of pins. list of registers and reset va lues in dtp/external interrupt figure 12.3-1 list of registers and reset values in dtp/external interrupt table 12.3-1 pins of dtp/external interrupt pin name pin function pin settings required for use in dtp/external interrupt p44/rx general-purpose i/o ports, can reception input set as input ports in port direction register (ddr) p24/int4 general-purpose i/o ports, dtp external interrupt inputs p25/int5 p26/int6 p27/int7 x: undefined bit151413121110 9 8 dtp/external interrupt factor register (eirr)xxxxxxxx bit76543210 dtp/external interrupt enable register (enir)00000000 bit151413121110 9 8 detection level setting register: high (elvr)00000000 bit76543210 detection level setting register: low (elvr)00000000 .com .com .com .com 4 .com u datasheet
332 chapter 12 dtp/external interrupt 12.3.1 dtp/external interrupt factor register (eirr) the dtp/external interrupt fact or register (eirr) holds dt p/external interrupt factors. when a valid signal is input to the dtp/external interrupt pin and the rx pin, the corresponding interrupt request flag bit is set to 1. dtp/external interrupt factor register (eirr) figure 12.3-2 dtp/external interrupt factor register (eirr) reset value xxxxxxxx b 12 13 11 10 9 8 bit 15 to bit 12, bit 8 14 15 r/w : read/write x : undefined - : unused r/w - - - r/w r/w r/w r/w 0 1 no dtp/external interrupt input dtp/ external interrupt input clears er bit no effect er7 to er4, er0 dtp/external interrupt request flag bits read write table 12.3-2 function of dtp/external interrupt factor register (eirr) bit name function bit 8, bit 12 to bit 15 er7 to er4, er0: dtp/external interrupt request flag bits these bits are set to 1 when the edges or level signals set by the detection condition select bits in the detection level setting register (elvr: lb, la) are input to the dtp/external interrupt pins and rx pin. when set to 1: when the dtp/external interr upt request enable bit (enir: en) is set to 1, an interrupt request is generated to the corresponding dtp/ external interrupt channel. when set to 0: cleared when set to 1: no effect note: reading by read-modify-write type instructions always reads "1". if more than one dtp/external in terrupt request is enabled (enir: en = 1), clear only th e bit in the channel that accepts an interrupt (eirr: er = 0). no other bits must be cleared unconditionally. reference: when the ei 2 os is started, the interrupt request flag bit is automatically cleared after the completion of data transfer (eirr: er = 0) bit 9 to bit11 unused bit read: the value is undefined write: no effect .com .com .com .com 4 .com u datasheet
333 chapter 12 dtp/external interrupt 12.3.2 dtp/external interrupt enable register (enir) the dtp/external interrupt enab le register (enir) enabl es/disables the dtp/external interrupt request for external interrupt pins (int7 to in t4) and the rx pin respectively. dtp/external interrupt enable register (enir) figure 12.3-3 dtp/external interrupt enable register (enir) 4 53210 6 7 r/w r/w r/w r/w r/w r/w r/w r/w bit 3 to bit 1 0 reset value 00000000 b bit 7 to bit 4, bit 0 r/w : read/write : reset value 0 1 en7 to en4, en0 dtp/external interrupt request enable bits dtp/external interrupt disable dtp/external interrupt enable re- served re- served re- served reserved reserved bits always set these bits to 0 table 12.3-3 functions of dtp/external interrupt enable register (enir) bit name function bit 0, bit 4 to bit 7 en7 to en4, en0: dtp/external interrupt request enable bits the dtp/external interrupt enable regi ster (enir) enables/disables the dtp/ external interrupt request for dtp/external interrupt pins (int7 to int4) and the rx pin. if the dtp/external interrupt request enable bit (enir: en) and the dtp/external interrupt request flag bit (eirr: er) are set to 1, the interrupt request is generated to the corresponding dtp/external interrupt pins or the rx pin. reference: the state of the dtp/external interr upt pin and the rx pin can be read directly using the port data regist er irrespective of the setting of the dtp/external interrupt request enable bit. table 12.3-4 correspondence among dtp/external interrupt pins, dtp/external interrupt request flag bits, and dtp/external interrupt request enable bits dtp/external interrupt pins dtp/external interrupt request flag bits dtp/external interrupt request enable bits rx er0 en0 int4 er4 en4 int5 er5 en5 int6 er6 en6 int7 er7 en7 .com .com .com .com 4 .com u datasheet
334 chapter 12 dtp/external interrupt 12.3.3 detection level setting register (elvr) (high) the detection level setting register (high) sets the levels or edges of input signals that cause interrupt factors in int7 to int4 of the dtp/ external interrupt pins. detection level setting register (elvr) (high) figure 12.3-4 detection level setting register (elvr) (high) reset value 00000000 b 12 13 11 10 9 8 bit 15 to bit 8 14 15 r/w : read/write : reset value r/w r/w r/w r/w r/w r/w r/w r/w 0 1 0 1 detects low level detects high level detects rising edge detects falling edge 0 0 1 1 lb7, la7 lb6, la6 lb5, la5 lb4, la4 detection condition select bits table 12.3-5 functions of detection level setting register (elvr) (high) bit name function bit 8 to bit 15 lb7, la7 to lb4, la4: detection condition select bits these bits set the levels or edges of input signals from external peripheral devices that cause interrupt factors in the dtp/external interrupt pins. two levels or two edges are selectab le for external interrupts, and two levels are selectable for the ei 2 os. reference: when the set detection signal is input to the dtp/external interrupt pins, the dtp/external interrupt request flag bits are set to 1 even if dtp/external interr upt requests are disabled (enir: en = 0). table 12.3-6 correspondence between detection level setting register (elvr) (high) and channels dtp/external interrupt pin bit name int4 lb4, la4 int5 lb5, la5 int6 lb6, la6 int7 lb7, la7 .com .com .com .com 4 .com u datasheet
335 chapter 12 dtp/external interrupt 12.3.4 detection level setting register (elvr) (low) the detection level setting register (elvr) (low) sets the levels or edges of input signals that cause interrupt factors in the rx pin. detection level setting register (elvr) (low) figure 12.3-5 detection level setting register (elvr) (low) 4 53210 bit1 bit0 6 7 r/w r/w r/w r/w r/w r/w r/w r/w 0 1 0 1 0 0 1 1 lb0, la1 0 bit 7 to bit 2 re- served re- served re- served re- served re- served re- served reserved reserved bits always set these bits to 0 reset value 00000000 b r/w : read/write : reset value detects low level detects high level detects rising edge detects falling edge detection condition select bits table 12.3-7 functions of detection level setting register (elvr) (low) bit name function bit 0 to bit 1 lb3, la0: detection condition select bits these bits set the levels or edges of input signals from external peripheral devices that cause interrupt factors in the rx pin. two levels or two edges are selectab le for external interrupts, and two levels are selectable for the ei 2 os. reference: when the set detection signal is input to the rx pin, the dtp/ external interrupt request flag bits are set to 1 even if dtp/ external interrupt requests ar e disabled (enir: en = 0). table 12.3-8 correspondence between detection level setting register (elvr) (low) and channels dtp/external interrupt pin bit name rx lb0, la0 .com .com .com .com 4 .com u datasheet
336 chapter 12 dtp/external interrupt 12.4 explanation of operation of dtp/external interrupt the dtp/external interrupt has an external interrupt f unction and a dtp function. the setting and operati on of each function are explained. setting of dtp/external interrupt using the dtp/external interrupt requires, the setting shown in figure 12.4-1. figure 12.4-1 setting of dtp/external interrupt setting procedure to use the dtp/external interrupt, set each register by using th e following procedure: 1. set the interrupt request enable bit corresponding to the dtp/external interrupt channel to be used to 0 (enir: en). 2. use the detection condition select bit corresponding to the dtp/external interrupt pin and the rx pin to be used to set the edge or level to be detected (elvr: la, lb). 3. set the interrupt request flag bit corresponding to the dtp/external interrupt channel to be used to 0 (eirr: er). 4. set the interrupt request enable bit corresponding to the dtp/external interrupt channel to be used to 1 (enir: en). when setting the registers for the dtp/external interr upt, the external interrupt request must be disabled in advance (enir: en = 0). when enabling the dtp/external interrupt request (enir: en = 1), the corresponding dtp/external interrupt request flag bit must be cleared in advan ce (eirr: er = 0). these act ions prevent the mistaken interrupt request from occurring when setting the register. bit1514131211109bit8bit7654321bit0 icr interrupt control register ics3 ics2 ics1 ics0 ise il2 il1 il0 ics3 ics2 ics1 ics0 ise il2 il1 il0 external interrupt dtp ---- 0 1 ---- 0 1 eirr/enir er7 er6 er5 er4 --- er0 en7 en6 en5 en4 re- served re- served re- served en0 --- 000 elvr lb7 la7 lb6 la6 lb5 la5 lb4 la4 re- served re- served re- served re- served re- served re- served lb0 la0 000000 ddr port direction register set the bit corresponding to pin used for dtp/external interrupt input to 0. ? : unused bit : used bit : set the bit corresponding to used pin to 1 0: set 0 1: set 1 .com .com .com .com 4 .com u datasheet
337 chapter 12 dtp/external interrupt selecting of dtp or external interrupt function whether the dtp function or the external interrupt function is executed depends on the setting of the ei 2 os enable bit in the corresponding in terrupt control register (icr: ise). if the ise bit is set to 1, the ei 2 os is enabled and the dtp function is executed. if the ise bit is set to 0, the ei 2 os is disabled and the external interrupt function is executed. dtp/external interrupt operation the control bits and the interrupt factors for the dtp/external in terrupt are shown in table 12.4-1. if the interrupt request from the dtp/external interrupt is output to the interrupt controller and the ei 2 os enable bit in the interrupt control register (icr: ise) is set to 0, the interrupt processing is executed. this bit is set to 1, the ei 2 os is executed. notes: all interrupt requests assigned to one interrupt control register have the same interrupt levels (il2 to il0). if two or more interrupt requests are assigned to one interrupt control register and the ei 2 os is used in one of them, other interrupt requests cannot be used. table 12.4-1 control bits and interrupt factors for dtp/external interrupt dtp/external interrupt interrupt request flag bit eirr: er7 to er4, er0 interrupt request enable bit enir: en7 to en4, en0 interrupt factor input of valid edge/level to int7 to int4, rx pins .com .com .com .com 4 .com u datasheet
338 chapter 12 dtp/external interrupt figure 12.4-2 shows the operation of the dtp/external interrupt. figure 12.4-2 operation of dtp/external interrupt acceptance determined by interrupt controller start interrupt processing microprogram dtp/external interrupt request generated interrupt acceptance determined by cpu start external interrupt clear processing and interrupt flag return from external interrupt transfer data between memory and resource update descriptor return from ei 2 os processing (dtp processing) icr : ise ei 2 os starts 0 = 0 0 1 elvr eirr enir icr yy icr xx dtp/external interrupt circuit factor cmp il ilm cmp interrupt processing interrupt processing other request interrupt controller cpu reset or stop descriptor data counter return from dtp processing .com .com .com .com 4 .com u datasheet
339 chapter 12 dtp/external interrupt 12.4.1 external interrupt function the dtp/external interrupt has an external interrupt function for generating an interrupt request by detecting the signal (edge or level ) in the dtp/external interrupt pin and the rx pin. external interrupt function when the signal (edge or level) set in the detection level setting register is detected in the dtp/external interrupt pin and the rx pin, the interrupt request fl ag bit in the dtp/external interrupt factor register (eirr: er) is set to 1. if the interrupt request enable bit in the dtp/external interrupt enable register is enabled (enir: en = 1) and the interrupt request flag bit set to 1, the interrupt is implemented to the interrupt controller. if an interrupt request is preferred to other interr upt request by the interrupt controller, the interrupt request is generated. if the level of an interrupt request (icr: il) is higher than that of the interrupt level mask bit (tlm) in the processor status (ps) and the interrupt enable bit is enab led (ps: ccr: i = 1) , the cpu performs interrupt processing after completion of the current instruction execution and branches to interrupt processing. at interrupt processing, set the corresponding dtp/exte rnal interrupt request flag bit to 0 and clear the dtp/external interrupt request. notes: when the dtp/external interrupt start factor is generated, the dtp/external interrupt request flag bit (eirr: er) is set to 1, regardless of the setting of the dtp/external interrupt request enable bit (enir: en). when the interrupt processing is st arted, clear the dtp/external inte rrupt request flag bit that caused the start factor. control cannot be returned from th e interrupt while the dtp/external interrupt request flag bit is set to 1. when clear ing, do not clear any flag bit ot her than the accepted dtp/external interrupt factor. .com .com .com .com 4 .com u datasheet
340 chapter 12 dtp/external interrupt 12.4.2 dtp function the dtp/external interrupt has t he dtp function that detects the signal of the external peripheral device from the dt p/external interrupt pin and the rx pin to start the ei 2 os. dtp function the dtp function detects the signal level set by the detection level setting register of the dtp/external interrupt function to start the ei 2 os. when the ei 2 os operation is already enable d (icr: ise = 1) at the point when the interrupt request is accepted by the cpu, the dt p function starts the ei 2 os and starts data transfer. when transfer of one data item is completed, the descriptor is updated and the dtp/external interrupt request flag bit is cleared to prep are for the next request from the dt p/external interrupt pin and the rx pin. when the ei 2 os completes transfer of all the data, control branches to the interrupt processing. figure 12.4-3 example of interface with external peripheral device input to int4 pin (dtp factor) internal operation of cpu descriptor selected/read high level request (elvr : lb4, la4 = 01 b ) descriptor updated dtp/external interrupt circuit cpu (ei 2 os) internal memory peripheral device external- connected data transfer request interrupt request internal data bus read/write operation* 2 dtp factor* 1 int *1: this must be cancelled within three machine cycles after the start of data transfer. *2: when ei 2 os is "peripheral function internal memory transfer". .com .com .com .com 4 .com u datasheet
341 chapter 12 dtp/external interrupt 12.5 precautions when using dtp/external interrupt this section explains t he precautions when using the dtp/external interrupt. precautions when using dt p/external interrupt condition of external-connected peripher al device when dtp function is used when using the dtp function, the peripheral device mu st automatically clear a data transfer request when data transfer is performed. inactivate the transfer request si gnal within three machine cycles af ter starting data transfer. if the transfer request signal remains active, the dtp/external interrupt regards the transfer request signal as a generation of next transfer request. external interrupt input polarity when the edge detection is set in the detection level setting register, the pulse width for edge detection must be at least three machine cycles. when a level causing an interrupt factor is input with level detection set in the detection level setting register, the interrupt request flag bit (eirr:er) of the dtp/external interrupt factor register is set to 1 and the factor is held as shown in figure 12.5-1. with the factor held in the interrupt request flag bit (eirr:er), the request to the interrupt controller remains active if the interrupt request is enabled (eni r: en = 1) even after th e dtp/external interrupt factor is cancelled. to cancel the re quest to the interrupt controller, clear the interrupt request flag bit (eirr:er) as shown in figure 12.5-2. figure 12.5-1 clearing interrupt request flag bit (eirr:er) when level set figure 12.5-2 dtp/external interrupt factor and interrupt request generated when interrupt request enabled dtp/interrupt input detector enable gate interrupt request flag bit (eirr:er) dtp/external interrupt factor to interrupt controller (interrupt request) the factor remains held unless cleared. dtp/external interrupt factor (when high level detected) interrupt request issued to interrupt controller the interrupt request is inactived by clearing the interrupt request flag bit (eirr:er) interrupt factor cancelled .com .com .com .com 4 .com u datasheet
342 chapter 12 dtp/external interrupt precautions on interrupts when the dtp/external interrupt is used as the external interrupt function, no return from interrupt processing can be made with the dtp/external interrupt request flag bit set to 1 (eirr: er) and the dtp/external interrupt request set to "enabled" (eni r: en = 1). always set the dtp/external interrupt request flag bit to 0 (eirr: er) at interrupt processing. when the level detection is set in the detection le vel setting register and the level that becomes the interrupt factor remains input, the dtp/external interrupt request flag bit is reset immediately even when cleared (eirr: er = 0). disable the dtp/external interrupt request output as needed (enir: en = 0), or cancel the interrupt factor itself. .com .com .com .com 4 .com u datasheet
343 chapter 12 dtp/external interrupt 12.6 program example of dtp/external interrupt circuit this section gives a program example of the dtp/exte rnal interrupt function. program example of dtp/ex ternal interrupt function processing specifications an external interrupt is generated by detecting the rising edge of the pulse input to the int4 pin. coding example icr0 6 equ 0000b 6 h ; dtp/external interrupt control register ddr2 equ 000012h ; port 2 direction register enir equ 000030h ; dtp/external interrupt enable register eirr equ 000031h ; dtp/external interrupt factor register elvrl equ 000032h ; detection level setting register: l elvrh equ 000033h ; detection level setting register: h er0 equ eirr:0 ; int4 interrupt request flag bit en0 equ enir:0 ; int4 interrupt request enable bit ; ;-----main program--------------------------------------------------------------- code cseg start: ; stack pointer (sp) already initialized mov i:ddr2,#00000000b ; ddr2 set to input port and ccr,#0bfh ; interrupts disabled mov i:icr0 6 ,#00h ; interrupt level 0 (highest) clrb i:er4 ; int4 disabled using enir mov i:elvrl,#00000010b ; rising edge selected for int4 clrb i:er4 ; int4 interrupt request flag ; cleared using eirr setb i:en4 ; int4 interrupt request enabled using enir mov ilm, #07h ; ilm in ps set to level 7 or ccr, #40h ; interrupts enabled loop: processing by user bra loop ;-----interrupt program---------------------------------------------------------- wari: clrb i:er4 ; interrupt request flag cleared processing by user reti ; return from interrupt processing code ends ;-----vector setting------------------------------------------------------------- vect cseg abs=0ffh org 00ffc0h ; vector set to interrupt number #15 (0f h ) dsl wari org 00ffdch ; reset vector set dsl start db 00h ; set to single-chip mode vect ends end start .com .com .com .com 4 .com u datasheet
344 chapter 12 dtp/external interrupt program example of dtp function processing specification channel 0 of the ei 2 os is started by detecting the high level of the signal input to the int4 pin. ram data is output to port 1 by performing dtp processing (ei 2 os). coding example icr0 6 equ 0000b 6 h ; dtp/external interrupt control register ddr1 equ 000011h ; port 1 direction register ddr5 equ 000015h ; port 5 direction register enir equ 000030h ; dtp/external interrupt enable register eirr equ 000031h ; dtp/external interrupt factor register elvrl equ 000032h ; detection level setting register: l elvrh equ 000033h ; detection level setting register: h er4 equ eirr:0 ; int4 interrupt request flag bit en4 equ enir:0 ; int4 interrupt request enable bit ; bapl equ 000100h ; buffer address pointer lower bapm equ 000101h ; buffer address pointer middle baph equ 000102h ; buffer address pointer higher iscs equ 000103h ; ei 2 os status register ioal equ 000104h ; i/o address register lower ioah equ 000105h ; i/o address register higher dctl equ 00010 6 h ; data counter lower dcth equ 000107h ; data counter higher ; ;-----main program--------------------------------------------------------------- code cseg start: ; stack pointer (sp) already initialized mov i:ddr1,#11111111b ; ddr1 set to output port mov i:ddr5,#00000000b ; ddr5 set to input port and ccr,#0bfh ; interrupts disabled mov i:icr0 6 ,#0 8 h ; interrupt level 0 (highest) ei 2 os ; channel 0 ; ; deta bank register (dtb) = 00h ; mov bapl,#00h ; address for storing output data set mov bapm,#0 6 h ; ( 6 00 h to 6 0a h used) mov baph,#00h mov iscs,#12h ; byte transfer, buffer address + 1 ; i/o address fixed, ; transfer from memory to i/o mov ioal,#00h ; port 0 (pdr0) set as mov ioah,#00h ; transfer destination address pointer mov dctl,#0ah ; transfer count set to 10 mov dcth,#00h ; clrb i:en4 ; int4 disabled using enir mov i:elvrl,#00010000b; h level detection set for int4 clrb i:er4 ; int4 interrupt request flag cleared using eirr setb i:en4 ; int4 interrupt request enabled using enir mov ilm,#07h ; ilm in ps set to level 7 or ccr,#40h ; interrupts enabled .com .com .com .com 4 .com u datasheet
345 chapter 12 dtp/external interrupt loop: processing by user bra loop ;-----interrupt program---------------------------------------------------------- wari: clrb i:er4 ; int4 interrupt request flag cleared processing by user reti ; return from interrupt processing code ends ;-----vector setting------------------------------------------------------------- vect cseg abs = 0ffh org 00ff9ch ; vector set to interrupt number #24 (1 8 h ) dsl wari org 00ffdch ; reset vector set dsl start db 00h ; set to single-chip mode set vect ends end start .com .com .com .com 4 .com u datasheet
346 chapter 12 dtp/external interrupt .com .com .com .com 4 .com u datasheet
347 chapter 13 8-/10-bit a/d converter this chapter explai ns the functio ns and operation of 8-/ 10-bit a/d converter. 13.1 overview of 8-/10-bit a/d converter 13.2 block diagram of 8-/10-bit a/d converter 13.3 configuration of 8-/10-bit a/d converter 13.4 interrupt of 8-/10-bit a/d converter 13.5 explanation of operation of 8-/10-bit a/d converter 13.6 precautions when using 8-/10-bit a/d converter .com .com .com .com 4 .com u datasheet
348 chapter 13 8-/10-bit a/d converter 13.1 overview of 8-/10-bit a/d converter the 8-/10-bit a/d converter conve rts the analog input voltage to a 8- or 10-bit digital value by using the rc sequentia l-comparison con verter system. an input signal can be selected from the input signals of the analog input pins for 8 channels. the start trigger can be selecte d from a softw are trigger, internal timer output, and an external trigger. function of 8-/10-bit a/d converter the 8-/10-bit a/d converter converts the analog voltage (input voltage) input to the analog input pin into an 8- or 10-bit digital value (a/d conversion). the 8-/10-bit a/d converter has the following functions: a/d conversion time is a minimum of 6.12 s * per channel including sampling time. sampling time is a minimum of 2.0 s per channel. * rc sequential-comparison converter system with sample & hold circuit setting of 8-bit or 10-bit resolution enabled analog input pin can be used up to 8 channels. generates interrupt request by storing a/d conversion results in a/d data register starts ei 2 os if interrupt request generated. use of the ei 2 os prevents data loss even at continuous conversion. selects start trigger from software trigger, intern al timer output, and extern al trigger (falling edge) *: when the machine clock fr equency operates at 16 mhz conversion modes of 8-/10-bit a/d converter there are conversion mo des of 8-/10-bit a/d converter as shown below: table 13.1-1 conversion modes of 8-/10-bit a/d converter conversion mode description single conversion mode a/d conversion is performed sequentia lly from the start channel to the end channel. when a/d conversion for th e end channel is terminated, it stops. continuous conversion mode a/d conversion is performed sequentia lly from the start channel to the end channel. when a/d conversion for the en d channel is terminated, it is continued after returning to the start channel. pause-conversion mode a/d conversion is performed sequentia lly from the start channel to the end channel. when a/d conversion for the en d channel is terminated, a/d conversion and pause are repeated after returning to the start channel. .com .com .com .com 4 .com u datasheet
349 chapter 13 8-/10-bit a/d converter 13.2 block diagram of 8-/10-bit a/d converter the 8-/10-bit a/d converter consists of following blocks. block diagram of 8-/10-bit a/d converter figure 13.2-1 block diagram of 8-/10-bit a/d converter inte int paus sts1 sts0 strt reserved busy a/d data register (adcr) ans2 md0 ans1 ans0 ane2 ane1 ane0 md1 controller d/a converter analog channel selector start selector avr avcc avss an0 an1 an2 an3 an4 an5 an6 an7 to adtg comparator sample & hold circuit st0 st1 ct1 ct0 ? d9 d8 s10 d5 d6 d4 d3 d2 d1 d0 d7 decoder interrupt request output to : internal timer output ? : unused reserved : always set to 0 : machine clock a/d control status register (adcs) 2 6 2 internal data bus 2 2 .com .com .com .com 4 .com u datasheet
350 chapter 13 8-/10-bit a/d converter details of pins in block diagram table 13.2-1 shows the actual pin names and interrup t request numbers of the 8-/10-bit a/d converter a/d control status registers (adcs) this register starts the a/d conversion function by software, selects the start tr igger for the a/d conversion function, selects the conversion mode, enables or di sables an interrupt reque st, checks and clears the interrupt request flag, temporarily stops a/d convers ion and checks the state during conversion, and sets the start and end channels for a/d conversion. a/d data registers (adcr) this register stores the a/d conv ersion results, and selects the co mparison time, sampling time, and resolution of a/d conversion. start selector this selector selects the trigger to start a/d conversion. an internal timer output or external pin input can be set as the start trigger. table 13.2-1 pins and interrupt request numbers in block diagram pin name/interrupt request number in block diagram actual pin name/interrupt request number adtg trigger input pin p37/adtg to internal timer output to (16-bit reload timer, 16-bit free-run timer) an0 analog input pin ch 0 p50/an0 an1 analog input pin ch 1 p51/an1 an2 analog input pin ch 2 p52/an2 an3 analog input pin ch 3 p53/an3 an4 analog input pin ch 4 p54/an4 an5 analog input pin ch 5 p55/an5 an6 analog input pin ch 6 p56/an6 an7 analog input pin ch 7 p57/an7 avr vref+ input pin avr av cc v cc input pin av cc av ss v ss input pin av ss interrupt request output #18 (12 h ) .com .com .com .com 4 .com u datasheet
351 chapter 13 8-/10-bit a/d converter decoder this decoder sets the a/d conversion start channel select bits and the a/d co nversion end channel select bits in the a/d control status register (adcs: ans2 to ans0 and ane2 to ane0) to select the analog input pin to be used for a/d conversion. analog channel selector this selector selects the pin to be used for a/d conversion from the 8-chan nel analog input pins by receiving a signal from the decoder. sample & hold circuit this circuit holds the input voltage selected by the analog channel selector. by holding the input voltage immediately after a/d conversion is started, a/d conversion is performed without being affected by the fluctuation of the input voltage during a/d conversion. d/a converter this converter generates the reference voltage which is compared with the input voltage held in the sample & hold circuit. comparator this comparator compares the d/a converter output voltage with input voltage held in the sample & hold circuit to determine the mount of voltage. controller this circuit determines the a/d c onversion value by recei ving the signal indicati ng the amount of voltage determined by the comparator. when the a/d conversion results are determined, the result data is stored in the a/d data register. if an interrupt request is enabled, an interrupt is generated. .com .com .com .com 4 .com u datasheet
352 chapter 13 8-/10-bit a/d converter 13.3 configuration of 8-/10-bit a/d converter this section explains the pins, registers, and interrupt factors of the a/d converter. pins of 8-/10-bit a/d converter the pins of the 8-/10-bit a/d converter serve as general-purpose i/o ports. table 13.3-1 shows the pin functions and the setting required for use of the 8-/10-bit a/d converter. table 13.3-1 pins of 8-/10-bit a/d converter function used pin name pin function setting required for use of 8-/10-bit a/d converter trigger input adtg general-purpose i/o port, external trigger input set as input port in port direction register (ddr). channel 0 an0 general-purpose i/o ports, analog inputs set as input ports in port direction register (ddr). input of analog signal enabled (ader: ade7 to ade0 = 11111111 b ) channel 1 an1 channel 2 an2 channel 3 an3 channel 4 an4 channel 5 an5 channel 6 an6 channel 7 an7 reference: see chapter 4 "i/o port" for the block diagram of pins. .com .com .com .com 4 .com u datasheet
353 chapter 13 8-/10-bit a/d converter list of registers and reset val ues of 8-/10-bit a/d converter figure 13.3-1 register and reset value of 8-/10-bit a/d converter generation of interrupt from 8-/10-bit a/d converter in the 8-/10-bit a/d converter, when the a/d conversion results are stored in the a/d data register (adcr), the interrupt request flag bit in the a/d contro l status register (adcs: in t) is set to 1. when an interrupt request is enabled (adcs: inte = 1), an interrupt is generated. x: undefined bit76543210 a/d control status register (high) (adcs: h) 00000000 bit151413121110 9 8 a/d control status register (low) (adcs: l) 00000000 bit76543210 a/d data register (high) (adcr: h) 00101xxx bit151413121110 9 8 a/d data register (low) (adcr: l) xxxxxxxx bit76543210 analog input enable register (ader) 11111111 .com .com .com .com 4 .com u datasheet
354 chapter 13 8-/10-bit a/d converter 13.3.1 a/d control status register (high) (adcs: h) the a/d control status regist er (high) (adcs: h) pr ovides the following settings: starting a/d conversi on function by software selecting start trigge r for a/d conversion storing a/d conversion result s in a/d data register to enable or disable interrupt request storing a/d conversion result s in a/d data register to check and clear interrupt request flag pausing a/d conversion and ch ecking state during conversion a/d control status regi ster (high) (adcs: h) figure 13.3-2 a/d control st atus register (high) (adcs: h) reset value 00000000 b 12 13 11 10 9 8 bit 8 14 15 strt 0 1 bit 9 reserved 0 r/w : read/write : reset value sts1 0 0 1 1 bit 11 0 1 paus bit 12 inte 0 1 bit 13 r/w w r/w r/w r/w r/w r/w r/w sts0 0 1 0 1 bit 10 0 1 int bit 14 0 1 busy bit 15 reserved bit always set to "0" a/d conversion software start bit does not start a/d conversion starts a/d conversion pause flag bit (this bit is enabled only when ei 2 os is used) a/d conversion does not pause a/d conversion pauses interrupt request enable bit interrupt request disable interrupt request enable interrupt request flag bit read write a/d conversion not terminated a/d conversion terminated clear to "0" no effect a/d conversion-on flag bit read write a/d conversion terminated (inactive state) a/d conversion in operation terminates a/d conversion forcibly no effect a/d conversion start trigger select bit starts software starts software or external trigger starts software or internal timer starts software, external trigger, or internal timer .com .com .com .com 4 .com u datasheet
355 chapter 13 8-/10-bit a/d converter table 13.3-2 function of each bit of a/d control status register (high) (adcs: h) bit name function bit 8 reserved: reserved bit always set this bit to 0. bit 9 strt: a/d conversion software start bit this bit starts the 8-/10-bi t a/d converter by software. when set to 1: starts 8-/10-bit a/d converter if a/d conversion pauses in the pause-co nversion mode, it is re sumed by writing 1 to the strt bit. when set to 0: invalid. the state remains unchanged. read: the byte/word command reads "1". the re ad-modify-write seri es commands read "0". note: do not perform forcible termination (busy = 0) and software start (strt = 1) of the 8-/10-bit a/d converter simultaneously. bit 10 bit 11 sts1, sts0: a/d conversion start trigger select bits these bits select the trigger to start the 8-/10-bit a/d converter. if two or more start triggers are set (sts1, sts0 "00 b "), the 8-/10-bit a/d converter is started by the first-generated start trigger. note: start trigger setting should be changed when the operati on of resource generating a start trigger is stopped. bit 12 paus: pause flag bit this bit indicates the a/d conver sion operating state when the ei 2 os function is used. the paus bit is enabled only when the ei 2 os function is used. a/d conversion pauses while the a/d conversion results are transferred from the a/d data register (adcr) to memory. when a/d conversion pauses, the paus bit is set to 1. after transfer of the a/d conversion results to memory, the 8-/10-bit a/d converter automatically resumes a/d conversion. when a/d conversion is started, the paus bit is cleared to 0. bit 13 inte: interrupt request enable bit this bit enables or disables ou tput of an interrupt request. when the interrupt request flag bit is set (int=1) with an interrupt request enabled (inte = 1), an interrupt request is generated. note: always set this bit to 1 when the ei 2 os function is used. bit 14 int: interrupt reque st flag bit this bit indicates that an in terrupt request is generated. when a/d conversion is terminated and its results are stored in the a/d data register (adcr), the int bit is set to 1. when the interrupt reque st flag bit is set (int = 1) w ith an interrupt request enabled (inte = 1), an interrupt request is generated. when set to 0: cleared when set to 1: no effect when ei 2 os function started: cleared note: to clear the int bit, write 0 when the 8-/10-bit a/d converter is stopped. bit 15 busy: a/d conversion-on flag bit this bit forcibly terminates the 8-/10-bit a/ d converter. when read, this bit indicates whether the 8-/10-bit a/d conv erter is operating or stopped. when set to 0: forcibly terminates 8-/10-bit a/d converter when set to 1: no effect read: 1 is read when the 8-/10-bit a/d converter is operating and 0 is written when the converter is stopped. note: do not perform forcibly termination (busy= 0) and software start (strt=1) of the 8-/10-bit a/d converter simultaneously. .com .com .com .com 4 .com u datasheet
356 chapter 13 8-/10-bit a/d converter 13.3.2 a/d control status register (low) (adcs: l) the a/d control status register (low) (adcs: l) provi des the following settings: selecting a/d conversion mode selecting start channel and en d channel of a/d conversion a/d control status regi ster (low) (adcs: l) figure 13.3-3 a/d control status register low (adcs: l) reset value 00000000 b 4 53210 6 7 r/w : read/write : reset value ane2 0 0 0 0 1 1 1 1 an0 pin an1 pin an2 pin an3 pin an4 pin an5 pin an6 pin an7 pin bit 2 r/w r/w r/w r/w r/w r/w r/w r/w ane2 0 0 0 0 1 1 1 1 ane1 0 0 1 1 0 0 1 1 bit 1 ane0 0 1 0 1 0 1 0 1 bit 0 ane1 0 0 1 1 0 0 1 1 ane0 0 1 0 1 0 1 0 1 0 0 0 0 1 1 1 1 bit 5 0 0 1 1 0 0 1 1 bit 4 0 1 0 1 0 1 0 1 bit 3 md1 0 0 1 1 bit 7 md0 0 1 0 1 bit 6 an0 pin an1 pin an2 pin an3 pin an4 pin an5 pin an6 pin an7 pin single conversion mode 1 (restartable during conversion) single conversion mode 2 (not-restartable during conversion) continuous conversion mode (not-restartable during conversion) pause-conversion mode (not-restartable during conversion) ans2 ans1 ans0 a/d conversion end channel select bits a/d conversion start channel select bits a/d conversion mode select bits inactive state read during a conversion read during a pause in stop conversion mode channel number currently being converted channel number just previously converted .com .com .com .com 4 .com u datasheet
357 chapter 13 8-/10-bit a/d converter table 13.3-3 function of each bit of a/d control status register (low) (adcs: l) (1/2) bit name function bit 0 to bit 2 ane2 to ane0: a/d conversion end channel select bits these bits set the channel at which a/d conversion is terminated. start channel < end channel: a/d conversion starts at channel set by a/d conversion start channel select bits ( ans2 to ans0) and terminates channel set by a/d conversion end channel select bits (ane2 to ane0) start channel = end channel: a/d conversion is performed only for one channel set by a/d converter end (= start) ch annel select bi ts (ane2 to ane0 = ans2 to ans0). start channel > end channel: a/d conversion is performed from channel set by a/d conversion start channel select bits (ans2 to ans0) to an7, and from an0 to channel set by a/d conversion end channel select b its (ane2 to ane0). continuous conversion mode and pause-conversion mode: when a/d conversion terminated at the channel set by the a/d conversion end channel select bits (ane2 to ane0), it returns to the channel set by the a/d conversion start channel sele ct bits (ans2 to ans0). note: do not set the a/d conversion end channe l select bits (ane2 to ane0) during a/ d conversion. bit 3 to bit 5 ans2 to ans0: a/d conversion start channel select bits these bits set the channel at which a/d conversion start. at read, the channel number under a/d conversion or a/d-co nverted immediately before a/d conversion pauses can be checked. and before a/d conversion star ts, the previous conversion channel number will be read even if these bits have been already set to the new value. these bits are initialized to "000 b " at reset. start channel < end channel: a/d conversion starts at channel set by a/d conversion start channel select bits ( ans2 to ans0) and terminates at channel set by a/d conversi on end channel select bits (ane2 to ane0). start channel = end channel: a/d conversion is performed only for one channel set by a/d conversion (= end) cha nnel select bi ts (ans2 to ans0 = ane2 to ane0). start channel > end channel: a/d conversion is performed from channel set by a/d conversion start channel select bits (ans2 to ans0) to an7, and from an0 to channel set by a/d conversion end channel select bi ts (ane2 to ane0). continuous conversion mode and pause-conversion mode: when a/d conversion terminates at the channel set by the a/d conversion end channel select bits (ane2 to ane0), it returns to the channel set by the a/d conversion start channel sele ct bits (ans2 to ans0). read (during a/d conversion): the channel numbers (7 to 0) under a/d conversion are read. read (during pause- conversion mode a nd temporary stop): at read during a pause, the channel num ber a/d-converted im mediately before a pause is read. note: do not set the a/d conversion start ch annel bits (ans2 to ans0) during a/d conversion. .com .com .com .com 4 .com u datasheet
358 chapter 13 8-/10-bit a/d converter bit 6 bit 7 md1, md0: a/d conversion mode select bits these bits set the a/d conversion mode. single conversion mode 1: the analog inputs from the start channel (adcs: ans2 to ans0) to the end channel (adcs: ane2 to ane0) are a/d-converted continuously. the a/d conversion pauses after a/d conversion for the end channel. this mode can be restar ted during a/d conversion. single conversion mode 2: the analog inputs from the start channel (adcs: ans2 to ans0) to the end channel (adcs: ane2 to ane0) are a/d-converted continuously. the a/d conversion after a/d conversion for the end channel. this mode cannot be rest arted during a/d conversion. continuous conversion mode: the analog inputs from the start channel (adcs: ans2 to ans0) to the end channel (adcs: ane2 to ane0) are a/d-converted continuously. when a/d conversion for the end channel is terminated, it is continued after returning to the analog input for the start channel. to terminate a/d conversion forcibly, write 0 to the a/d conversion-on flag bit in the a/d control status register (adcs: busy). this mode cannot be rest arted during a/d conversion. pause conversion mode: a/d conversion for the start channel (adcs: ans2 to ans0) starts. the a/d conversion pauses at termination of a/d co nversion for a channel. when the start trigger is input while a/d co nversion pauses, a/d conversion for the next channel is started. the a/d conversion pauses at the terminati on of a/d conversion for the end channel. when the start trigger is input while a/d conversion pauses, a/d conversion is continued after returning to the analog input for the start channel. to terminate a/d conversion forcibly, write 0 to the a/d conversion-on flag bit in the a/d control status register (adcs: busy). this mode cannot be rest arted during a/d conversion. note: when the conversion mode is set to "not restartable" (md1, md0 "00 b "), it cannot be restarted with any start triggers (software tri gger, internal timer, and external trigger) during a/d conversion. table 13.3-3 function of each bit of a/d control status register (low) (adcs: l) (2/2) bit name function .com .com .com .com 4 .com u datasheet
359 chapter 13 8-/10-bit a/d converter 13.3.3 a/d data register (high) (adcr: h) the higher five bi ts in the a/d data r egister (adcr: h) se lect the compare time, sampling time and resoluti on of a/d conversion. bits 9 and 8 in the a/d data regi ster (adcr) are e xplained in section "13.3.4 a/d data register (low) (adcr: l)". a/d data register (high) (adcr: h) figure 13.3-4 a/ d data register (high) (adcr: h) reset value 00101xxx b 12 13 11 10 9 8 14 15 *1 : the parenthesized values are provided when the machine clock operates at 8-mhz. *2 : the parenthesized values are provided when the machine clock operates at 16-mhz. * : bit 8 and bit 9 are explained in "a/d data register (low) (adcr: l)". ct1 0 0 1 1 44/ (5.5 s) *1 66/ (4.12 s) *2 88/ (5.5 s) *2 176/ (11.0 s) *2 bit 12 0 0 1 1 st1 0 1 0 1 st0 20/ (2.5 s) *1 32/ (2.0 s) *2 48/ (3.0 s) *2 128/ (8.0 s) *2 bit 14 bit 13 s10 0 1 10 bits (d9 to d0) 8 bits (d7 to d0) bit 15 r r * * w ? w w w w ct0 0 1 0 1 bit 11 r : read only w : write only x : undefined ? : unused : machine clock : reset value compare time select bits sampling time select bits resolution select bits .com .com .com .com 4 .com u datasheet
360 chapter 13 8-/10-bit a/d converter table 13.3-4 functions of a/d data register (high) (adcr: h) bit name function bit 11 bit 12 ct1, ct0: compare time select bits these bits set the a/d conversion compare time. these bits set the time required from when analog input is a/d-converted until it is stored in the data bits (d9 to d0). note: the setting of ct1 and ct0 = "00 b " is based on operation at 8 mhz. setting based on operation at 16 mhz does not assure normal operation. when these bits are read, "00 b " is read. bit 13 bit 14 st1, st0: sampling time select bits these bits set the a/d conversion sampling time. these bits set the time required from when a/d conversion starts until the input analog voltage is sampled and held by the sample & hold circuit. note: the setting of st1 and st0 = "00 b " is based on operation at 8 mhz. setting based on operation at 16 mhz does not assure normal operation. when these bits are read, "00 b " is read. bit 15 s10: resolution select bit this bit selects the a/d conversion resolution. when set to 0: sets a/d conversion resolution in 10 bits from a/d conversion data bits d9 to d0. when set to 1: sets a/d conversion resolution in 8 bits from a/d conversion data bits d7 to d0. note: change the s10 bit in the pausing st ate before starting a/d conversion. changing the s10 bit after a/d co nversion starts disables the a/ d conversion results stored in the a/d conversion data bits (d9 to d0). .com .com .com .com 4 .com u datasheet
361 chapter 13 8-/10-bit a/d converter 13.3.4 a/d data register (low) (adcr: l) the a/d data register (low ) (adcr: l) stores the a/d conversion results. bits 8 and 9 in the a/d dat a register (adcr) are explained in this section. a/d data register (low) (adcr: l) figure 13.3-5 a/d data register (low) (adcr: l) r: read only x: undefined bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset value d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 xxxxxxxx b rrrrrrrrrr table 13.3-5 functions of a/d data register (low) (adcr: l) bit name function bit 0 to bit 9 d9 to d0: a/d conversion data bits these bits store the a/d conversion results. when resolution set in 10 bits (s10 = 0): conversion data is stored in the 10 bits from d9 to d0. when resolution set in 8 bits (s10 = 1): conversion data is stored in the 8 bits from d7 to d0. note: use a word instruction (movw) to read the a/d conversion results stored in the a/d conversion data bits (d9 to d0). .com .com .com .com 4 .com u datasheet
362 chapter 13 8-/10-bit a/d converter 13.3.5 analog input enable register (ader) the analog input enable register ( ader) enables or di sables the analog input pins to be used in the 8-/10-bi t a/d converter. analog input enable register (ader) figure 13.3-6 analog input enable register (ader) ane0 0 1 reset value 11111111 b 4 53210 bit 0 r/w r/w r/w r/w r/w r/w r/w r/w 6 7 ane1 0 1 bit 1 ane2 0 1 r/w : read/write : reset value bit 2 ane3 0 1 bit 3 ane4 0 1 bit 4 ane5 0 1 bit 5 ane7 0 1 bit 7 ane6 0 1 bit 6 analog input enable bit 0 (an0) analog input disable analog input enable analog input enable bit 1 (an1) analog input disable analog input enable analog input enable bit 2 (an2) analog input disable analog input enable analog input enable bit 3 (an3) analog input disable analog input enable analog input enable bit 4 (an4) analog input disable analog input enable analog input enable bit 5 (an5) analog input disable analog input enable analog input enable bit 6 (an6) analog input disable analog input enable analog input enable bit 7 (an7) analog input disable analog input enable .com .com .com .com 4 .com u datasheet
363 chapter 13 8-/10-bit a/d converter table 13.3-6 functions of analog input enable register (ader) bit name function bit 0 to bit 7 ade7 to ade0: analog input enable bits these bits enable or disa ble the analog input of the pin to be used for a/d conversion. when set to 0: disables analog input when set to 1: enables analog input notes: the analog input pins serve as a general-purpose i/o port of the port 5. when using the pin as an analog input pin, switch the pin to analog input pin according to the setting of the port 5 direction register (ddr5) and the analog input enable register (ader). when using the pin as an analog input pin, write 0 to the bit in the port 5 direction register (ddr5) corresponding to the pin to be used and turn off th e output transistor. also write 1 to the bit in the analog input en able register (ader) corresponding to the pin to be used and set the pin to analog input. .com .com .com .com 4 .com u datasheet
364 chapter 13 8-/10-bit a/d converter 13.4 interrupt of 8-/10-bit a/d converter when a/d conversion is termina ted and its results are stored in the a/d data register (adcr), the 8-/10- bit a/d converter generates an interr upt request. the ei 2 os function can be used. interrupt of a/d converter when a/d conversion of the analog input voltage is te rminated and its results ar e stored in the a/d data register (adcr), the interrupt request flag bit in the a/d control status register (adcs: int) is set to 1. when the interrupt request flag bit is set (adcs: int = 1) with an interrupt request output enabled (adcs: inte = 1), an interrupt request is generated. 8-/10-bit a/d converter interrupt and ei 2 os see section "3.5 interrupt" for details of the inte rrupt number, interrupt control register, and interrupt vector address. ei 2 os function of 8-/1 0-bit a/d converter in the 8-/10-bit a/d converter, the ei 2 os function can be used to tran sfer the a/d conversion results from the a/d data register (adcr) to memory. if the ei 2 os function is used, the a/d-converted data protection function is activated to cause a/d conversion to pause during memory transfer and prevent data loss as a/d conversion is performed continuously. .com .com .com .com 4 .com u datasheet
365 chapter 13 8-/10-bit a/d converter 13.5 explanation of operation of 8-/10-bit a/d converter the 8-/10-bit a/d converter has the following a/d conver sion modes. set each mode according to the setting of the a/d conversion mode select b its in the a/d control status register (adcs: md1, md0). single conversion mode (restartable/not -restartable during a/d conversion) continuous conversion mode (not-r estartable during a/d conversion) pause conversion mode ( not-restartable dur ing a/d conversion) single conversion mode ( adcs: md1, md0 = "00 b " or "01 b ") when the start trigger is input, the analog inputs from the start channel (adc s: ans2 to ans0) to the end channel (adcs: ane2 to ane0) are a/d-converted continuously. the a/d conversion stops at the termination of the a/d conversion for the end channel. to terminate a/d conversion forcib ly, write 0 to the a/d conversion -on flag bit in the a/d control status register (adcs: busy). when the a/d conversion mode select bits (md1, md0) are set to "00 b ", this mode can be restarted during a/d conversion. if the bits are set to 01 b , this mode cannot be restarted during a/d conversion. continuous conversion mode (adcs: md1, md0 = "10 b ") when the start trigger is input, the analog inputs from the start channel (adc s: ans2 to ans0) to the end channel (adcs: ane2 to ane0) are a/d-converted continuously. when a/d conversion for the end channel is terminated, it is continued after returning to the analog input for the start channel. to terminate a/d conversion forcib ly, write 0 to the a/d conversion -on flag bit in the a/d control status register (adcs: busy). this mode cannot be restarted during a/d conversion. pause-conversion mode (a dcs: md1, md0 = "11 b ") when the start trigger is input, a/d conversion starts for the start channel (adcs: ans2 to ans0). the a/d conversion pauses at the termination of a/d co nversion for one channel. when the start trigger is input while a/d conversion pauses, a/d conversion is performed for the next channel. the a/d conversion pauses at termination of a/d conv ersion for the end channel. when the start trigger is input while a/d conversion pauses, a/d conversion is continued after returning to the analog input for the start channel. to terminate a/d conversion forcib ly, write 0 to the a/d conversion -on flag bit in the a/d control status register (adcs: busy). this mode cannot be restarted during a/d conversion. .com .com .com .com 4 .com u datasheet
366 chapter 13 8-/10-bit a/d converter 13.5.1 single conversion mode in the single conversion mode , a/d conversion is performe d sequentially from the start channel to the end channel. the a/d conversion stops at the termination of a/d conversion for the end channel. setting of single conversion mode operating the 8-/10-bit a/d converter in the single conversion mode requires the setting shown in figure 13.5-1. figure 13.5-1 setting of single conversion mode operation of single conversion mode when the start trigger is input, a/d conversion star ts from the channel set by the a/d conversion start channel select bits (ans2 to ans0) and is performed continuously up to the channel set by the a/d conversion end channel select bits (ane2 to ane0). the a/d conversion stops at the termination of the a/d conversion for the channel set by the a/d conversion end channel select bits (ane2 to ane0). to terminate a/d conversion forcib ly, write 0 to the a/d conversion -on flag bit in the a/d control status register (adcs: busy). when the a/d conversion mode select bits (md1, md0) are set to "00 b ", this mode can be restarted during a/d conversion. if the bits are set to "01 b ", this mode cannot be restarted during a/d conversion. [when start and end channels are the same] if the start and end channels have the same cha nnel number (adcs: ans2 to ans0 = adcs: ane2 to ane0), only one a/d conversion for one channel set as the start channel (= en d channel) is performed and terminated. ? : unused : used bit : set the bit corresponding to pin to be used as analog input pin to 1. 0: set 0 bit1514131211109bit 8bit 7654321bit0 adcs busy int inte paus sts1 sts0 strt re- served md1 md0 ans2 ans1 ans0 ane2 ane1 ane0 00 adcr s10 st1 st0 ct1 ct0 ? d9 to d0(converted data stored) ader .com .com .com .com 4 .com u datasheet
367 chapter 13 8-/10-bit a/d converter [conversion order in single conversion mode] table 13.5-1 gives an example of the conversion order in the single conversion mode. table 13.5-1 conversion order in single conversion mode start channel end channel conversion order an0 pin (adcs: ans = "000 b ") an3 pin (adcs: ane = "011 b ") an0 --> an1 --> an2 --> an3 --> end an6 pin (adcs: ans = "110 b ") an2 pin (adcs: ane = "010 b ") an6 --> an7 --> an0 --> an1 --> an2 --> end an3 pin (adcs: ans = "011 b ") an3 pin (adcs: ane = "011 b ") an3 --> end .com .com .com .com 4 .com u datasheet
368 chapter 13 8-/10-bit a/d converter 13.5.2 continuous conversion mode in the continuous conversion mode, a/d con version is performed sequentially from the start channel to the end channel. when a/d conversion for the e nd channel is terminated, it is continued after returning to the start channel. setting of continuous conversion mode operating the 8-/10-bit a/d converter in the contin uous conversion mode requires the setting shown in figure 13.5-2. figure 13.5-2 setting of continuous conversion mode operation of continuous conversion mode when the start trigger is input, a/d conversion star ts from the channel set by the a/d conversion start channel select bits (ans2 to ans0) and is performed continuously up to the channel set by the a/d conversion end channel select bits (ane2 to ane0). when a/d conversion for the channel set by the a/d conversion end channel select bits (ane2 to ane0) is terminated, it is continued after returning to the channel set by the a/d conversion start channel select bits (ans2 to ans0). to terminate a/d conversion forcib ly, write 0 to the a/d conversion -on flag bit in the a/d control status register (adcs: busy). this mode cannot be restarted during a/d conversion. [when start and end channels are the same] if the start and end channels have the same cha nnel number (adcs: ans2 to ans0 = adcs: ane2 to ane0), a/d conversion for one channel set as th e start channel (= end channel) is repeated. ? : unused : used bit : set the bit corresponding to pin to be used as analog input pin to 1. 1: set 1 0: set 1 bit1514131211109bit 8bit 7654321bit0 adcs busy int inte paus sts1 sts0 strt re- served md1 md0 ans2 ans1 ans0 ane2 ane1 ane0 010 adcr s10 st1 st0 ct1 ct0 ? d9 to d0 (converted data stored) ader .com .com .com .com 4 .com u datasheet
369 chapter 13 8-/10-bit a/d converter [conversion order in cont inuous conversion mode] table 13.5-2 gives an example of the conversi on order in the continuous conversion mode. table 13.5-2 conversion order in continuous conversion mode start channel end channel conversion order an0 pin (adcs: ans = "000 b ") an3 pin (adcs: ane = "011 b ") an0 --> an1 --> an2 --> an3 --> an0 --> repeat an6 pin (adcs: ans = "110 b ") an2 pin (adcs: ane = "010 b ") an6 --> an7 --> an0 --> an1 --> an2 --> an6 --> repeat an3 pin (adcs: ans = "011 b ") an3 pin (adcs: ane = "011 b ") an3 --> an3 --> repeat .com .com .com .com 4 .com u datasheet
370 chapter 13 8-/10-bit a/d converter 13.5.3 pause-conversion mode in the pause-conversion mode , a/d conversion starts and pauses repeatedly for each channel. when the start trig ger is input afte r the a/d conversi on pauses at the termination of the a/d conversion for the en d channel, a/d conversi on is continued after returning to th e start channel. setting of pause-conversion mode operating the 8-/10-bit a/d converter in the pause- conversion mode requires the setting shown in figure 13.5-3. figure 13.5-3 setting of pause-conversion mode operation of paus e-conversion mode when the start trigger is input, a/d conversion starts at the channel set by the a/d conversion start channel select bits (ans2 to ans0). the a/d c onversion pauses at the termination of the a/d conversion for one channel. when the start trig ger is input while a/d conversion pauses, a/d conversion for the next channel is performed. the a/d conversion pauses at the termination of the a/d conversion for the channel set by the a/d conversion end channel select bits (ane2 to ane0 ). when the start trigger is input while a/d conversion pauses, a/d conversion is continued after returning to the channel set by the a/d conversion start channel select bits (ans2 to ans0). to restart this mode while a/d conversion pauses, input the start trigger set by the a/d start trigger select bits in the a/d control status register (adcs: sts1, sts0). to terminate a/d conversion forcib ly, write 0 to the a/d conversion -on flag bit in the a/d control status register (adcs: busy). this mode cannot be restarted during a/d conversion. ? : unused : used bit : set the bit corresponding to pin to be used as analog input pin to 1. 1: set 1 0: set 1 bit1514131211109bit 8bit 7654321bit0 adcs busy int inte paus sts1 sts0 strt re- served md1 md0 ans2 ans1 ans0 ane2 ane1 ane0 011 adcr s10 st1 st0 ct1 ct0 ? d9 to d0 (converted data stored) ader .com .com .com .com 4 .com u datasheet
371 chapter 13 8-/10-bit a/d converter [when start and end channels are the same] if the start and end channels have the same cha nnel number (adcs: ans2 to ans0 = adcs: ane2 to ane0), a/d conversion for one channel set as the star t channel (= end channel), and pause are repeated. [conversion order in pause-conversion mode] table 13.5-3 gives an example of the conve rsion order in the pause-conversion mode. table 13.5-3 conversion order in pause-conversion mode start channel end channel conversion order an0 pin (adcs: ans = "000 b ") an3 pin (adcs: ane="011 b ") an0 --> stop, start --> an1 --> stop, start --> an2 --> stop, start --> an3 --> stop, start --> an0 --> repeat an6 pin (adcs: ans = "110 b ") an2 pin (adcs: ane="010 b ") an6 --> stop, start --> an7 --> stop, start --> an0 --> stop, start --> an1 --> stop, start --> an2 --> stop, start --> an6 --> repeat an3 pin (adcs: ans = "011 b ") an3 pin (adcs: ane="011 b ") an3 --> stop, start --> an3 --> stop, start --> repeat .com .com .com .com 4 .com u datasheet
372 chapter 13 8-/10-bit a/d converter 13.5.4 conversion using ei 2 os function the 8-/10-bit a/d converter can transfer the a/d conversion result to memory by using the ei 2 os function. conversion using ei 2 os the use of the ei 2 os enables the a/d-converted data protection function to transfer multiple data to memory without the loss of converted data even if a/d conversion is performed continuously. the conversion flow when the ei 2 os is used is shown in figure 13.5-4. figure 13.5-4 flow of conversion when using ei 2 os a/d converter starts sample & hold a/d conversion starts a/d conversion terminates interrupt generated ei 2 os starts converted data transferred interrupt processing interrupt cleared specified count completed? * * : the specified count depends on the setting of the ei 2 os. yes no .com .com .com .com 4 .com u datasheet
373 chapter 13 8-/10-bit a/d converter 13.5.5 a/d-converted data protection function a/d conversion with the out put an interrupt request en abled activa tes the a/d conversion data protection function. a/d-converted data protection funct ion in 8-/10-bit a/d converter the 8-/10-bit a/d converter has only one a/d data regi ster (adcr) where a/d-converted data is stored. when the a/d conversion results are determined after the termination of a/d conversion, data in the a/d data register is rewritten. therefor e, the a/d conversion results may be lost if the a/d conversion results already stored are not read before data in the a/d data register is rewritten. the a/d-converted data protection function in the 8-/10-bit a/d converter is activated to prevent data loss. this function automatically causes a/d conversion to pause when an interrupt request is generated (adcs: int = 1) with an interrupt request enabled (adcs: inte = 1). a/d-converted data protection function when ei 2 os not used when the a/d conversion results are stored in the a/ d data register (adcr) af ter the analog input is a/ d-converted, the interrupt request flag bit in the a/d control status register (adcs: int) is set to 1. a/d conversion pauses for data protection while the interrupt request flag bit in the a/d control status register (adcs: int) is set. when the int bit is set with an interrupt request from the a/d control status register enabled (adcs: inte = 1), an interrupt request is generated. when the int bit is cleared by the generated interrupt processing, the pause of a/d conversion is cancelled. a/d-converted data protection function when ei 2 os used a/d conversion pauses for data protection while the ei 2 os function is used to transfer the a/d conversion results to memory from the a/d data re gister after a/d conversi on. when a/d conversion pauses, the pause flag bit in the a/d control status register (adcs: paus) is set to 1. when the transfer of the a/d conve rsion results to memory by the ei 2 os function is terminated, the pause of a/d conversion is cancelled and the pause flag bit (adcs: paus) is cleared to 0. if a/d conversion is performed continuously, it is restarted. processing flow of a/d conversion data protection function when ei 2 os used figure 13.5-5 shows the processing flow of the a/d conversion data protection function when the ei 2 os is used. .com .com .com .com 4 .com u datasheet
374 chapter 13 8-/10-bit a/d converter figure 13.5-5 processing flow of a/d co nversion data protection function when using ei 2 os ei 2 os set a/d continuous conversion starts first conversion terminates data in a/d data register stored second conversion terminates ei 2 os starts note: the operation flow of when the a/d converter is stopped is omitted. data in a/d data register stored third conversion entire conversion terminates ei 2 os terminates a/d pauses ei 2 os starts ei 2 os starts a/d conversion pauses no yes interrupt processing continued start end notes: the a/d conversion data protection function is activated only when an interrupt request is enabled. set the interrupt request enable bit in the a/d control status register (adcs: inte) to 1. when the ei 2 os function is used to transfer the a/d co nversion results to memory, do not disable output of an interrupt request. if output of an interrupt request is disabled during a pause of a/d conversion (adcs: inte = 0), a/d conversion may be restarted to rewrite data being transferred. when the ei 2 os function is used to transfer the a/d co nversion results to memory, do not restart. restarting during a pause of a/d conversion may cause loss of the a/d conversion results. .com .com .com .com 4 .com u datasheet
375 chapter 13 8-/10-bit a/d converter 13.6 precautions when using 8-/10-bit a/d converter precautions when using the 8-/10-bit a/d convert er are given below: precautions when using 8- /10-bit a/d converter analog input pin the analog input pins serve as general-purpose i/o ports of port 5. when using the pin as an analog input pin, switch the pin to "analog input pin" accord ing to the setting of the port 5 direction register (ddr5) and the analog input enable register (ader). when using the pin as an analog input pin, write 0 to the bit in the ddr5 corresponding to the pin to be used and turn off the output transistor. also write 1 to the bit in the ader corresponding to the pin to be used and set the pin to "analog input enable." when an intermediate-level signal is input with the pin set as a general-purpose i/o port, the input leakage current flows in the gate. when using the pi n as an analog input pin, always set the pin to "analog input enable". precaution when starting by internal timer or external trigger the input value at which the 8-/10-bit a/d converter is started by the internal timer output or external trigger should be set to "inactive" (high for external trigger). holding the input value for the start trigger active may cause the 8-/10-bit a/d converter to start concurrently with the setting of the a/d start trigger select bits in the a/d contro l status register (adcs: sts1, sts0). procedure of 8-/10-bit a/d converter and analog input power-on always apply a power to the a/d converter power (av cc , avr) and the analog input (an0 to an7) after or concurrently with the digital power (v cc )-on. always turn off the a/d converter power and the analog input before or concurrently with the digital power (v cc )-down. note that avr should not exceed av cc at power on or power down. (there is no problem to turn on or off the analog power and digital power concurrently.) power supply voltage of 8-/10-bit a/d converter to prevent latch up, note that the 8-/10-bit a/d converter power (av cc ) should not exceed the digital power (v cc ) voltage. .com .com .com .com 4 .com u datasheet
376 chapter 13 8-/10-bit a/d converter .com .com .com .com 4 .com u datasheet
377 chapter 14 uart1 this chapter explai ns the functio n and operat ion of the uart. 14.1 overview of uart1 14.2 block diagram of uart1 14.3 configuration of uart1 14.4 interrupt of uart1 14.5 baud rate of uart1 14.6 explanation of operation of uart1 14.7 precautions when using uart1 14.8 program example for uart1 .com .com .com .com 4 .com u datasheet
378 chapter 14 uart1 14.1 overview of uart1 the uart1 is a general-purpos e serial-data commu nication interfac e for synchronous or asynchronous communication wi th external devices. incorporates a bidirectional communication function (clock synchr onous and asynchronous modes) incorporates a master /slave type commu nication function (in multiprocessor mode: only master) capable of generating an interrupt request at completion of tr ansmit completion and receive completion, and at detection of a receive error supports expansion intelligent i/o service (ei 2 os) function of uart1 function of uart1 the uart1 is a general-purpose serial-data communi cation interface, which transmits/receives serial data with external devices. uart1 has functions listed in table 14.1-1. table 14.1-1 function of uart1 function data buffer full-duplicate double-buffer transfer mode synchronous to clock (without start bit/stop bit and parity bit) asynchronous (start-stop synchronization to clock) baud rate dedicated baud-rate generator (the baud rate can be selected from among eight types.) any baud rate can be set by external clock. a clock supplied from the internal clock (16-bit reload timer 1) can be used. data length 7 bits (for asynchronous normal mode only) 8 bits signal type nrz (non return to zero) type detection of receive error framing error overrun error parity error (not supported for operation mode 1) interrupt request receive interrupt (receive, de tection of receive error) transmit interrupt (transmit) both the transmission and reception support ei 2 os. master/slave type communication function (asynchronous multiprocessor mode) this function enables communicati ons between 1 (only use master) and n (slave) (this function is used only as the master side) note: at the clock synchronous transfer, the uart only transfers data, not affixing the start and stop bits. .com .com .com .com 4 .com u datasheet
379 chapter 14 uart1 table 14.1-2 operation mode of uart1 operation mode data length synchronous/ asynchronous length of stop bit with parity no parity 0 asynchronous mode (normal mode) 7 or 8 bits asynchronous 1 bit or 2 bits *2 1 multiprocessor mode 8 + 1 *1 ? asynchronous 2 synchronous mode 8 ? synchronous none ? : setting disabled *1: +1 is the address/data select bit (scr1 register bit 11: a/d) used for controlling communications. *2: during reception, only one bit can be detected as the stop bit. .com .com .com .com 4 .com u datasheet
380 chapter 14 uart1 14.2 block diagram of uart1 the uart1 consists of the following block. block diagram of uart1 figure 14.2-1 block diagram of uart1 control bus sin1 sck1 sot1 start of reception receive interrupt request output receive clock transmit interrupt request output md1 md0 cs2 cs1 scke soe tdre bds clock selector dedicated baud rate generator internal data bus serial mode register 1 serial status register 1 serial control register 1 pin pin pin pen p sbl cl a/d rec rxe 16-bit reload timer start bit detector receive controller receive bit counter receive shift register receive parity counter serial input data register 1 end of reception transmit start circuit transmit controller transmit bit counter transmit shift register transmit parity counter serial output data register 1 transmit clock cs0 txe rie tie pe ore fre rdrf reception state determine circuit receive-error- generate signal for ei 2 os (to cpu) rst md div2 div1 div0 communi- cation prescaler control register .com .com .com .com 4 .com u datasheet
381 chapter 14 uart1 details of pins, etc., in block diagram the actual pin names and interrupt request numbers used in the uart1 are as follows: sin1 pin: p40/sin1 sck1 pin: p41/sck1 sot1 pin: p42/sot1 transmit interrupt number 1: #38 (26 h ) receive interrupt number 1: #37 (25 h ) clock selector the clock selector selects the transm it/receive clock from the dedicated ba ud rate generator, external input clock, and internal clock (clock supplied from 16-bit reload timer). receive controller the receive controller is composed of receive bit counter, start bit detect or and receive parity counter. the receive bit counter counts the receive data, and outputs a receive interr upt request when reception of one piece of data is completed accordin g to the specified data length. the start bit detector detects the st art bit from the serial input signal and writes th e received data to the serial input data register (sidr1), on a bit-by-bit shift basis in accordance with the transfer rate. the receive parity counter detects parity bit of the receive data. transmit controller the transmit controller is composed of the transmit bit counter, transmit start circuit, and transmit parity counter. the transmit bit counter counts the transm it data, and outputs a transmit interrupt request when transmission of one piece of data is completed according to the set data length. the transm it start circuit starts transmission when serial ou tput data register (sodr1) is written. the transmit parity counter generates the parity bit of the data transferred when parity is provided. receive shift register the receive shift register writes th e receive data input from the sin pi n while shifting b it-by-bit, and when the data reception is completed, it transfers the r eceive data to the serial in put data register (sidr1). transmit shift register data written to sodr1 is transferred to the transmit shift register itself, and then the data is output to the sot pin while shifting bit-by-bit. .com .com .com .com 4 .com u datasheet
382 chapter 14 uart1 serial mode register 1 (smr1) this register: selects operation mode selects clock input source (baud rate) sets dedicated baud rate generator selects clock speed (clock division value) when using dedicated baud rate generator enables or disables output of serial data and clock pins initialize uart serial control register 1 (scr1) this register: sets availability of parity selects type of parity sets stop bit length sets data length selects frame data format in operation mode 1 (asynchronous multiprocessor mode) clears error flag enables or disables transmitting enables or disables receiving serial status register 1 (ssr1) the status register checks the transm ission/reception state and error state and sets enabling/disabling of the transmit/receive interrupt request. serial input data register 1 (sidr1) the serial input data register retains the receive data. the serial input data is co nverted and then stored in this register. serial output data register 1 (sodr1) the serial output data register sets the transmit data. data written to this register is serial-converted and then output. communication prescaler control register (cdcr) the control register sets the baud rate of the baud rate generator, which sets the start/stop of the communication prescaler and the di vision rate of machine clock. .com .com .com .com 4 .com u datasheet
383 chapter 14 uart1 14.3 configuration of uart1 the uart1 pins, interrupt factors, register list and details are shown. uart1 pin the pins used in the uart1 se rve as general-purpose i/o port. table 14.3-1 indicates the pin functions and the setting necessary for use in the uart1. block diagram of pins of uart1 see "chapter 4 i/o port" for the block diagram of pins. list of registers in uart1 figure 14.3-1 list of registers and reset values in uart1 table 14.3-1 uart1 pin pin name pin function setting necessary for use in uart1 sot1 general-purpose i/o port, serial data output set to output enable. (smr1 register bit 0: soe=1) sck1 general-purpose i/o port, serial clock input/output in clock input, set pin as input port in port direction register (ddr). in clock output, set to output enable. (smr1 register bit 1: scke=1) sin1 general-purpose i/o port, serial data input set pin as input port in ddr. x: undefined bit151413121110 9 8 serial control register 1 (scr1) 0 0 0 0 0 1 0 0 bit76543210 serial mode register 1 (smr1) 0 0 0 0 0 0 0 0 bit151413121110 9 8 serial status register 1 (ssr1) 0 0 0 0 1 0 0 0 bit76543210 serial input data register 1 (sidr1)/ serial output data register 1 (sodr1) xxxxxxxx note: function as sidr1 when readin g, function as sodr1 when writing bit151413121110 9 8 communication prescaler control register 1 (cdcr1) xxxxxxxx .com .com .com .com 4 .com u datasheet
384 chapter 14 uart1 interrupt request g eneration by uart1 receive interrupt when receive data is loaded to the serial input data register (sidr1), the receive data load flag bit (bit 12: rdrf) in the serial status regist er (ssr1) is set to 1. when a recei ve interrupt is en abled (bit 9: rie = 1), a receive interrupt request is generated to the interrupt controller. when either a framing error, overrun error, or pari ty error occurs, the frami ng error flag bit (bit 13: fre), the overrun error flag bit (bit 14: ore), or pa rity error flag bit (bit 15: pe) in the serial status register (ssr1) are set to 1 accord ing to the error occurred. when a receive interrupt is enabled (bit 9: rie = 1), a receive interrupt is re quested to the interrupt controller. transmit interrupt when transmit data is transferred from the serial output data register (sodr1) to the transmit shift register, the transmit data empty flag bit (bit 11: tdre) in the serial status register (ssr1) is set to 1. if a transmit interrupt is enabled (bit 8: tie = 1), a transmit interrupt is requested to the interrupt controller. .com .com .com .com 4 .com u datasheet
385 chapter 14 uart1 14.3.1 serial control register 1 (scr1) the serial control register 1 ( scr1) performs the following: setting parity bit, selecting stop bit length and data length, selecting frame data format in operation mode 1 (asynchronous multiprocessor mode), clea ring receive error fl ag, and enabling/ disabling of transmitting/receiving. serial control r egister 1 (scr1) figure 14.3-2 serial control register 1 (scr1) txe 0 1 reset value 00000100 b 12 13 11 10 9 8 bit 8 r/w r/w w r/w r/w r/w r/w r/w 14 15 rxe 0 1 bit 9 rec 0 1 clear pe and ore, fre, bits no effect r/w : read/write w : write only : reset value bit 10 a/d 0 1 bit 11 cl 0 1 7 bits 8 bits bit 12 sbl 0 1 bit 13 pen 0 1 p bit 15 bit 14 0 1 transmit enable bit transmit disable transmit enable receive enable bit receive disable receive enable receive error flag clear bit data frame address frame address/data select bit data-length select bit 1-bit length 2-bit length stop-bit length select bit no parity with parity parity addition enable bit enable only when parity provided (pen = 1) even parity odd parity parity select bit .com .com .com .com 4 .com u datasheet
386 chapter 14 uart1 table 14.3-2 function of serial control register 1 (scr1) bit name function bit 8 txe: transmit enable bit enable or disable the uart1 for sending. when set to 0: transmission disabled when set to 1: transmission enabled note: when transmitting is disabled during transmitting, transmitting stops after the data in the serial output data register (sodr1) being transmitted is completed. to set this bit to 0, after writing data to sodr1, wait for a time of 1/16th of the baud rate in the asynchronous mode and for a time equal to or more than the baud rate in the synchronous mode. bit 9 rxe: receive enable bit enable or disable the uart1 for receiving. when set to 0: reception disabled when set to 1: reception enabled note: when receiving is disabled during recei ving, receiving stops after the data being received is stored in th e serial input data register. bit 10 rec: receive error flag clear bit clear the receive error flags (bit 15 to 13 : pe, ore and fre) of the serial status register (ssr1) to 0. when set to 0: clears pe, ore and fre bits when set to 1: no effect when read: 1 always read note: when a receive interrupt is enabled (bit 9: rie = 1), set the bit10: rec bit to 0 only when any one of the pe, ore and fre bits is set to 1. bit 11 a/d: address/data select bit in operation mode 1 (asynchronous multipro cessor mode), set the data format of the frame to be transmitted/received. when bit set to 0: data frame set when bit set to 1: address frame set bit 12 cl: data-length select bit specify the length of send and receive data. note: a data length of 7 bits can be selected only in operation mode 0 (asynchronous normal mode). in ope ration modes 1 and 2 (asynchronous multiprocessor mode, clock synchronous mode), be sure to set a data length of 8 bits. bit 13 sbl: stop-bit length select bit set the length of the stop bit (frame end mark of send data) in operation modes 0 and 1 (multiprocessor mode, synchronous mode). note: at receiving, only the first bit of the stop bit is always detected. bit 14 p: parity select bit select either odd or even parity when with parity (pen = 1) is set. bit 15 pen: parity addition enable bit specify whether to add (a t sending) and detect (at receiving) a parity bit. note: a parity bit is not added in operation modes 1 and 2 (multiprocessor mode, synchronous mode). be sure to set this bit to 0. .com .com .com .com 4 .com u datasheet
387 chapter 14 uart1 14.3.2 serial mode register 1 (smr1) the serial mode register 1 (smr1) performs selecting oper ation mode, selecting baud rate clock, and disabling /enabling of output of ser ial data and clock to pin. serial mode register 1 (smr1) figure 14.3-3 serial mode register 1 (smr1) md1 md0 mode no. 0 1 0 1 0 0 1 1 0 1 2 ? reset value 00000000 b 4 5 63210 7 bit6 asynchronous mode (normal mode) asynchronous multiprocessor mode clock synchronous mode setting disable operation mode select bits operation mode soe 0 1 serves as general-purpose i/o port serves as serial data output of uart1 serial data output enable bit (sot1 pin) bit 0 scke 0 1 0 1 serves as general-purpose i/o port or clock input pin of uart 1 serves as serial clock output pin of uart1 serial clock i/o enable bit (sck1 pin) bit 1 rst no effect initialize all registers of uart1 uart reset bit bit 2 bit 5 bit 4 bit 3 cs2 cs1 cs0 baud rate by dedicated baud rate generator baud rate by internal timer (16-bit reload timer1) baud rate by external clock "000 b " to "100 b " "110 b " "111 b " clock input source select bits bit 7 r/w : read/write : reset value r/w r/w r/w r/w r/w r/w r/w r/w .com .com .com .com 4 .com u datasheet
388 chapter 14 uart1 table 14.3-3 function of serial mode register 1 (smr1) bit name function bit 0 soe: serial-data output enable bit enable or disable output of serial data. when set to 0: general-purpose i/o port set when set to 1: serial data output pin set bit 1 scke: serial clock i/o enable bit switch between input and output of the serial clock. when set to 0: general-purpose i/o port or serial clock input pin set when set to 1: serial clock output pin set notes: 1. when using the sck1 pin as the se rial clock input, set the pin to the input port using the port direction register (ddr). also select the external clock (bit 5 to 3: cs2 to cs0 = "111 b ") using the clock input source select bit. 2. when using the sck pin as the serial clock output, set the clock input source select bit to anything other than the external clock (bit 5 to 3: cs2 to cs0 = anything other than "111 b "). bit 2 rst: uart reset bit this bit resets all registers in the uart1. when set to 0: no effect on operation when set to 1: resets all registers in uart1 bit 3 to bit 5 cs0 to cs2: clock input source select bits set the clock input source for the baud rate. select the external clock (sck1 pin), internal timer (16-bit reload timer), or dedicated baud rate generator as the clock input source. set the baud rate when selectin g the dedicated baud rate generator. bit 6 and bit 7 md0, md1: operation mode select bits select the uart1 operation mode. notes: 1. in operation mode 1 (asynchronous multiprocessor mode), only the master can be used for master/s lave communication. in operation mode 1, the address/data bit on bit 9 cannot be received, so the slave cannot be used. 2. in operation mode 1 (asynchronous multiprocessor mode), the parity check function cannot be used, set the parity addition enable bit to no parity (scr1 register bit 15: pen = 0). note: when 0 is written to the rst bit of serial mode register, the uart interruption should be prohibited. to prohibit the interruption, take one of the following procedures: 1. before writing 0 to the rst bit, clear i flag to prohibit all interrupt factors. 2. before writing 0 to the rst bit, prohibit the uart interruption with the ilm register. 3. when 0 is written to the rst bit, writing shoul d be performed at the uart interruption level or the level with higher priority than the uart interruption. .com .com .com .com 4 .com u datasheet
389 chapter 14 uart1 14.3.3 serial status register 1 (ssr1) the serial status register 1 (ssr1) checks the transmission/recept ion status and error status and enables/disables interrupts. serial status register 1 (ssr1) figure 14.3-4 serial status register 1 (ssr1) tie 0 1 disables transmit interrupt enables transmit interrupt transmit interrupt enable bit reset value 00001000 b 12 13 11 10 9 8 bit 8 14 15 rie 0 1 disables receive interrupt enables receive interrupt receive interrupt enable bit bit 9 tdre 0 1 with transmit data (write of transmit data disabled) no transmit data (write of transmit data enabled) transmit data writing flag bit bit 11 rdrf 0 1 no receive data with receive data receive data load flag bit bit 12 fre 0 1 no framing error with framing error framing error flag bit bit 13 no overrun error with overrun error overrun error flag bit pe 0 1 no parity error with parity error parity error flag bit bit 15 bit 14 ore 0 1 r/w r/w r/w r r r r r r/w : read/write r : read only : reset value bds 0 1 lsb first (transfer from least significant bit) msb first (transfer from most significant bit) transfer direction select bit bit 10 .com .com .com .com 4 .com u datasheet
390 chapter 14 uart1 table 14.3-4 function of serial status register 1 (ssr1) bit name function bit 8 tie: transmit interrupt enable bit enable or disable send interrupt. when set to 1: a receive interrupt request is issued when data wri tten to the serial output data register 1 (sodr1) is sent to the transmit shift register (bit 11: tdre = 1). bit 9 rie: receive interrupt enable bit enable or disable receive data. when set to 1: a receive interrupt request is issued when receive data is loaded to the serial input data register 1 (sidr1) (bit 12: rdrf = 1) or when a receive error occurs (bit 15: pe = 1, bit 14: ore = 1, or bit 13: fre = 1). bit 10 bds: transfer direction select bit this bit sets the direction of serial data transfer. when set to 0: transfers data from least significant bit (lsb first) when set to 1: transfers data from most significant bit (msb first) note: at reading and writing data from and to the se rial data register, data is written to the serial output data register (sodr1) and then the transfer direction select bit (bds) is rewritten to switch betwee n the upper bits and the lower bi ts of data. in this case, the written data becomes invalid. bit 11 tdre: transmit data write flag bit show the status of the seri al output data register 1. this bit is cleared to 0 when send data is written to the serial out put register 1(sodr1). this bit is set to 1 when data is loaded to the send shift register and transmission starts. when a transmission interrupt is enabled (bit 8: tie = 1), a transmit interrupt request is issued when data written to the serial output data register 1(sodr1) is transmitted to the transmit shift register (bit 11: tdre=1). bit 12 rdrf: receive data load flag bit show the status of the serial input data register 1 (sidr1). this bit is set to 1 when receive data is loaded to the serial input register 1 (sidr1). this bit is cleared to 0 when data is read from the sidr1. when a receive interrupt is enabled (bit 9: ri e = 1), a receive interru pt request is issued when receive data is loaded to the serial input data register 1 (sidr1). bit 13 fre: framing error flag bit detect a framing error in receive data. this bit is set to 1 when a framing error occurs. this bit is cleared when 0 is written to the receive error flag clear bit (scr1 register bit 10: rec). when a receive interrupt is enabled (bit 9: ri e = 1), a receive interru pt request is issued when a framing error occurs. when the framing error flag bit is set (bit 13: fre = 1), data in th e serial input data register 1 (sidr1) is invalid. bit 14 ore: overrun error flag bit detect an overrun error in receiving. this bit is set to 1 when an overrun error occurs. this bit is cleared when 0 is written to the receive error flag clear bit (scr1 register bit 10: rec). when a receive interrupt is enabled (bit 9: ri e = 1), a receive interru pt request is issued when an overrun error occurs. when the overrun error flag bit is set (bit 14: ore = 1), data in th e serial input data register 1 (sidr1) is invalid. bit 15 pe: parity error flag bit detect a parity error in receiving. this bit is set to 1 when a parity error occurs. this bit is cleared when 0 is written to the receive error flag clear bit (scr1 register bit 10: rec). when a receive interrupt is enabled (bit 9: ri e = 1), a receive interru pt request is issued when a parity error occurs. when the parity error flag bit is set (bit 15: pe = 1), data in the seri al input data register 1 (sidr1) is invalid. .com .com .com .com 4 .com u datasheet
391 chapter 14 uart1 14.3.4 serial input data register 1 (sidr1) and serial output data register 1 (sodr1) the serial input data register (sidr1) and serial output data register (sodr1) are allocated to the same address. at read, th e register functions as sidr1. at write, the register functions as sodr1. serial input data register 1 (sidr1) figure 14.3-5 serial input data register 1 (sidr1) sidr1 is a data buffer register for receiving serial data. the serial data signal transmitted to the serial data input pin (sin1) is converted by the shift register and stored in sidr1. when the data length is 7 bits, the upper one bit (sidr1: d7) becomes invalid. when receive data is stored in the serial input data register 1 (sidr1 ), the receive data load flag bit (ssr1 register bit 12: rdrf) is set to 1. when a recei ve interrupt is enabled (ssr1 register bit 9: rie = 1), a receive interrupt request is issued to the interrupt controller. read sidr1 when the receive data load flag bit (s sr1 register bit 12: rdrf) is set to 1. the receive data load flag bit (ssr1 register bit 12: rdrf) is cleared to 0 automatically when sidr1 is read. when a receive error occurs (any one of ssr1 re gister bit 15, 14, 13: pe, ore and fre is 1), the receive data in sidr1 becomes invalid. r: read only x: undefined bit 7654321bit 0reset value d7 d6 d5 d4 d3 d2 d1 d0 xxxxxxxx b rrrrrrrr .com .com .com .com 4 .com u datasheet
392 chapter 14 uart1 serial output data register 1 (sodr1) figure 14.3-6 serial output data register 1 (sodr1) the serial output data register 1 (sodr1) is a data buffer register for transmitting serial data. when data to be transmitted is written to sodr1 when transmission is enabled (scr1 register bit 8: txe = 1), it is transferred to the transmit shift regi ster, converted to serial data, and transmit from the serial data output pin (sot1). when the data length is 7 bits, the upper one bit (sodr1 register bit 7: d7) becomes invalid. the transmit data write flag (ssr1 register bit 11: tdre) is cleared to 0 when send data is written to sodr1. the transmit data write flag is set to 1 at completion of data transfer to the transmit shift register. when the transmit data write flag (ssr1 register bit 11: tdre) is 1, the next transmit data can be written. when a transmit interrupt is enabled (ssr1 register bit 8: tie=1), a transmit interrupt occurs to the interrupt controller. the next transmit bit data should be written with the transmit data write flag (scr1 register bit 11: tdre) at 1. w: write only x: undefined 7654321bit 0reset value d7 d6 d5 d4 d3 d2 d1 d0 xxxxxxxx b wwwwwwww note: serial output data register is a write-only register and serial input data regist er is a read-only register. however, since they are allocated to the same address, the write and read values are different. therefore, do not use instructions that perform read-modify -write (rmw) operation such as inc and dec instructions. .com .com .com .com 4 .com u datasheet
393 chapter 14 uart1 14.3.5 communication prescaler control register 1 (cdcr1) the communication prescaler contro l register 1 (cdcr1) is used to set the baud rate of the dedicated baud rate ge nerator for the uart1. starts/stop the co mmunication prescaler sets the division ratio for machine clock communication prescaler cont rol register 1 (cdcr1) figure 14.3-7 communication pres caler control register 1 (cdcr1) reset value 0xxx0000 b 12 13 14 11 10 9 8 15 bit 10 bit 9 div2 div1 communication prescaler division ratio (div) bits 1-divided clock 2-divided clock 3-divided clock 4-divided clock 5-divided clock 6-divided clock 7-divided clock 8-divided clock bit 8 div0 r/w : read/write x : undefined ? : unused : reset value 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 reserved 0 always set 0 reserved bit bit 11 md 0 1 communication prescaler stopped communication prescaler enabled communication prescaler control bit bit 15 r/w r/w r/w r/w ? ? ? r/w .com .com .com .com 4 .com u datasheet
394 chapter 14 uart1 table 14.3-5 functions of communication prescaler control register 1 (cdcr1) bit name function bit 8 to bit 10 div0 to div2: communication prescaler division ratio bits these bits set the machine clock division ratio. note: when changing the division ratio, the time of at least 2 cycles division of the division clock should be allowed before the next communication is started in order to stabilize the clock frequency. bit 11 reserved: reserved bit be sure to set this bit to 0. bit 12 to bit 14 unused bits read: the value is not fixed. write: no effect bit 15 md: communication prescaler control bit this bit enables or disables the communication prescaler. when set to 0: stops communication prescaler when set to 1: operates comm unication prescaler .com .com .com .com 4 .com u datasheet
395 chapter 14 uart1 14.4 interrupt of uart1 the uart1 has a receive and a transmit interr upts, and the following factors can issue interrupt requests. receive data is loaded to the serial input dat a register 1 (sidr1). a receive error (parity error, overrun error, framing error) occurs. when send data transferred from the serial out put data register 1 (sodr1) to transmit shift register also, each of these interr upt factors supports the expans ion intelligent i/o service (ei 2 os). interrupt of uart1 the uart1 interrupt control bits and inte rrupt factors are show n in table 14.4-1. table 14.4-1 uart1 interrupt control bit and interrupt factor trans-mission/ reception interrupt- request flag bit operation mode interrupt factor interrupt factor enable bit clear of the interrupt- request flag 012 reception ssr1: rdrf ?? receive data loaded into serial input data register 1 (sidr1) ssr1: rie reading receive data ssr1:ore ?? overrun error writing 0 to receive error flag clear bit (scr1 register bit 10: rec) ssr1:fre ? x framing error ssr1:pe x x parity error transmission ssr1: tdre ?? transfer of transmit data completed from serial output data register 1 (sodr1) ssr1: tie writing transmit data : available x: not available .com .com .com .com 4 .com u datasheet
396 chapter 14 uart1 receive interrupt when a receive interrupt is enabled (ssr1 register bit 9: rie = 1), a r eceive interrupt request is issued to the interrupt controller at completion of data receivi ng (ssr1 register bit 12: rdrf = 1) or when any one of the overrun error (ssr1 register bit 14: ore = 1), framing error (ssr 1 register bit 13: fre = 1), and parity error (ssr 1 register bit 15: pe = 1) occurs. the receive data load flag (ssr1 regi ster bit 12: rdrf) is cleared to 0 automatically when the serial input data register 1 (sidr1) is read. e ach receive error flag (ssr1 register bit 15, 14, 13: pe, ore, fre) is cleared to 0 when 0 is written to the receive er ror flag clear bit (scr1 register bit 10: rec). transmit interrupt when send data is transmitted from the serial output data register 1 (sodr1) to the transmit shift register, the transmit data write flag bit (ssr1 register bit 11: tdre) is set to 1. when a transmit interrupt is enabled (ssr1 register bit 8: tie = 1), a send interrupt request is issued to the interrupt controller. interrupt relat ed to uart1 and ei 2 os see section "3.5 interrupt" for th e interrupt number, interrupt cont rol register, and interrupt vector addresses. ei 2 os function of uart1 the uart1 supports ei 2 os. consequently, ei 2 os can be started separately for receive interrupts and transmit interrupts. at reception: the ei 2 os can be used regardless of the state of other resources. at transmission: since the interrupt control registers (icr13, 14) are shared with transmit interrupts of uart1, ei 2 os can be started only when uart1 receive interrupts are not used. note: if a receive error (par ity error, overrun error, framing error) o ccurs, correct the error as necessary, and then write 0 to the receive error flag clear bit (scr1 register bit 10: re c) to clear each receive error flag. .com .com .com .com 4 .com u datasheet
397 chapter 14 uart1 14.4.1 generation of receive interrupt and timing of flag set interrupts at receiving include the receive comple tion (ssr1 register bit 12: r drf), and the receive error (ssr1 register bit 15, 14, 13: pe, ore, fre). generation of receive interr upt and timing of flag set receive data load flag and each receive error flag sets when data is received, it is stored in the serial input data register 1 (sidr1) when the stop bit is detected (in operation modes 0 and 1: asynchronous normal mode, asynchronous multiprocessor mode) or when the last bit of receive data (sidr1 register bit 7: d7) is detected (in operation mode 2: clock synchronous mode). when a receive error occurs, the error flags (ssr1 register bit 15, 14 , 13: pe, ore, fre) and receive data load flag (ssr1 regist er bit 12: rdrf) are set. in each operation mode, the received data in the serial input data register 1 (sidr1) is invalid if either error flag is set. operation mode 0 (async hronous normal mode) the receive data load flag bit (ssr 1 register bit 12: rdrf) is set when the stop bit is detected. the error flags (ssr1 register bit 15, 14, 13: pe, ore, fre) are set when a receive error occurs. operation mode 1 (asynchronous multiprocessor mode) the receive data load flag bit (ssr 1 register bit 12: rdrf) is set when the stop bit is detected. the error flags (ssr1 register bit 14, 13: ore, fre) are set when a receive error occurs. a parity error (ssr1 register bit 15: pe) cannot be detected. operation mode 2 (clock synchronous mode) the receive data load flag bit (ssr 1 register bit 12: rdrf) is set to 1 when the last bit of receive data (sidr1 register bit 7: d7) is det ected. the error flags (ssr 1 register bit 14: ore) are set when a receive error occurs. a parity error (ssr1 register bit 15: pe ) and framing error (ssr1 register bit 13: fre) cannot be detected. reception and timing of flag se t are shown in figure 14.4-1. .com .com .com .com 4 .com u datasheet
398 chapter 14 uart1 figure 14.4-1 reception and timing of flag set timing of receive interrupt request generation with a receive interrupt enabled (ssr 1 register bit 9: rie = 1), when a ny one of the receive data load flag (ssr1 register bit 12: rdrf), parity error flag (ssr1 register bit 15: pe), overrun error flag (ssr1 register bit 14: ore) and framing error flag (s sr1 register bit 13: fre) is se t, reception interrupt is requested to interrupt controller. ssr1: pe, ore, fre* receive interrupt occurs receive data (operation mode 0) receive data (operation mode 1) receive data (operation mode 2) ssr1: rdrf d0 d1 d6 d7 a/d sp st d0 d1 sp st d0 d1 d4 d5 d6 d7 d5 d6 d7 * : the pe flag cannot be detected in operation mode 1. the pe and fre flags cannot be detected in operation mode 2. st : start bit sp : stop bit a/d : address/data select bit of operation mode 2 .com .com .com .com 4 .com u datasheet
399 chapter 14 uart1 14.4.2 generation of transmit interrupt and timing of flag set at transmission, the interrupt is generated in the state which the succeeding data can be written to the serial output data register 1 (sodr1). generation of transmit interr upt and timing of flag set set and clear of transmit data empty flag bit the send data write flag bit (ssr1 register bit 11: td re) is set when the send data written to the serial output data register 1 (sodr1) is loaded to the send shift register and the next data is ready for writing. the send data write flag bit (ssr1 register bit 11: tdre ) is cleared to 0 when the next send data is written to the serial output data register 1 (sodr1). transmission and timing of flag set are shown in figure 14.4-2. figure 14.4-2 transmission and timing of flag set timing of transmit interrupt request when a transmit interrupt is enabled (ssr1 register bit 8: tie = 1), a send interrupt request is issued to interrupt controller when the transmit data write flag bit (ssr1 register bit 11: tdre) is set. st : start bit d0 to d7 : data bits sp : stop bit a/d : address/data select bit d2 d3 d5 d6 d4 st d0 d1 st d0 d2 d3 d1 d7 sp a/d sp writing to sodr1 transmit interrupt requested transmit interrupt occured [operation modes 0 and 1] ssr1: tdre output to sot1 d3 d4 d6 d7 d5 d0 d1 d2 d3 d4 d6 d7 d5 d0 d1 d2 writing to sodr1 [operation mode 2] ssr1: tdre output to sot1 transmit interrupt occured transmit interrupt occured note: when sending is disabled during sending (scr1 regi ster bit 8: txe=0: and also in operation mode 1 (asynchronous multiprocessor mode), receiving disabled (also includin g bit 9: rxe), the send data write flag bit is set (ssr1 register bit 11: tdrf=1) and uart 1 communications are disabled after the shift operation of the send shift register stops. the send data written to the serial output data register 1 before the transmission stops (sodr1) is sent. .com .com .com .com 4 .com u datasheet
400 chapter 14 uart1 14.5 baud rate of uart1 one of the following can be selected as the uart1 transmit/receive clock. dedicated baud rate generator internal clock (16-bit reload timer output) external clock (clock input to sck1 pin) select of uart1 baud rate the uart1 baud rate select circuit comprises as shown in figure 14.5-1. the clock input source can be selected from among th e following three types: baud rate by dedicated baud rate generator when using the dedicated baud rate generator incorporated into uart1 as a clock input source, set the cs2 to cs0 bits in the serial mode register (smr1) bit 5 to 3 to "000 b " to "101 b " according to the baud rate. the baud rate can be selected from six types. baud rate by internal timer when using the internal clock supplied from the 16-b it reload timer as a clock input source, set the cs2 to cs0 bits in smr1 bit 5 to 3 to "110 b ". the baud rate is the value at which the clock supplied from the 16-bit reload timer as it is in the clock synchronous mode, and the value at which the frequency of the supplied clock is divided by 16 in the clock asynchronous mode. any baud rate can be selected according to th e setting values of the 16-bit reload timer. baud rate by external clock when using the external clock supplied from the clock input pin (sck1) in the uart1 as the clock input source, set the cs2 to cs0 bits in smr1 bit 5 to 3 to "111 b ". the baud rate is the value at which the external cl ock is supplied in the clock synchronous mode and the value at which the frequency of the input clock is divided by 16 in the clock asynchronous mode. .com .com .com .com 4 .com u datasheet
401 chapter 14 uart1 figure 14.5-1 uart1 baud rate selector pin oscillation dividing circuit [clock synchronous] any one of the 1/1, 1/2, 1/4, 1/8, 1/16, 1/32 division ratio is selected [asynchronous] the internal fixed division ratio is selected /1, /2, /3, /4, /5, /6, /7, /8 clock selector communication prescaler (cdcr1: md0, div2 to div0) smr1: cs2 to cs0 (clock input source select bits) tmcsr1: csl1, csl0 uf sck1 1/1 [clock synchronous] 1/16 [asynchronous] 1/1 [clock synchronous] 1/16 [asynchronous] clock selector decrement counter prescaler baud rate cs2 to cs0 = "110 b " cs2 to cs0 = "111 b " cs2 to cs0 = "000 b " to "101 b " 16-bit reload timer 1 smr1: md1, md0 (operation mode select bits) [external clock] [internal timer] [dedicated baud rate generator] /2 1 /2 3 /2 5 : machine clock uf : underflow .com .com .com .com 4 .com u datasheet
402 chapter 14 uart1 14.5.1 baud rate by dedicated baud rate generator the baud rate that can be set when the out put clock of t he dedicated baud rate generator is selected as th e transmit/receive clock of the uart1 is shown. baud rate by dedicated baud rate generator the baud rate based on the dedicated baud rate generator is set by setting the clock input source select bits in the serial mode register (smr1 regi ster bit 5 to 3: cs2 to cs0) to "000 b " to "101 b ". when generating a transmit/receive cloc k using the dedicated baud rate ge nerator, the division ratio for the clock input source selected by the cl ock selector is selected to determ ine the baud rate after the machine clock frequency is divided by the communication prescaler. the division ratio at which the machine clock frequency is divided by the communication prescaler is the same for the clock synchronous and asynchronous mode s. the division ratio at which the baud rate is determined is different for the clock synchronous and asynchronous modes. figure 14.5-2 shows the baud rate selector based on the dedicated baud rate generator. figure 14.5-2 baud rate selector based on dedicated baud rate generator calculation expression for baud rate baud rate in asynchronous mode = x div x (division ratio of transfer clock in asynchronous mode) baud rate in clock synchronous mode = x div x (division ratio of transfer clock in clock synchronous mode) : machine clock frequency div: division ratio based on communication prescaler dividing circuit [clock synchronous] any one of the 1/1, 1/2, 1/4, 1/8, 1/16, 1/32 division ratio is selected [asynchronous] the internal fixed division ratio is selected /1, /2, /3, /4, /5, /6, /7, /8 clock selector communication prescaler (cdcr1: md0, div2 to div0) baud rate smr1: md1, md0 (operation mode select bits) smr1: cs2 to cs0 (clock input source select bits) : machine clock frequency .com .com .com .com 4 .com u datasheet
403 chapter 14 uart1 division ratio based on communication presca ler (common between asynchronous and clock synchronous modes) the division ratio of the machine clock is set by the division ratio select bits in the communication prescaler control register (cdcr1 regi ster bit 10 to 8: div2 to div0). baud rate (asynchronous mode) the baud rate in the asynchronous mode is generated using output clock of the communication prescaler. the division ratio is set by the clock input source sel ect bits (smr1 register bit 5 to 3: cs2 to cs0). table 14.5-1 division ratio based on communication prescaler md div2 div1 div0 div 0 ??? stop 10001 10012 10103 10114 11005 11016 11107 11118 div: division ratio based on communication prescaler table 14.5-2 baud rate (asynchronous mode) cs2 cs1 cs0 asynchronous mode (start/stop synchronous) calculation 0 0 0 76,923 bps ( /div) / (8 x 13 x 2) 0 0 1 38,461 bps ( /div) / (8 x 13 x 4) 0 1 0 19,230 bps ( /div) / (8 x 13 x 8) 0 1 1 9,615 bps ( /div) / (8 x 13 x 16) 1 0 0 500 kbps ( /div) / (8 x 2 x 2) 1 0 1 250 kbps ( /div) / (8 x 2 x 4) : machine clock frequency div: division ratio based on communication prescaler .com .com .com .com 4 .com u datasheet
404 chapter 14 uart1 baud rate (synchronous mode) the baud rate in the synchronous mode is generated by dividing the output clock of the communication prescaler by 1, 2, 4, 8, 16 and 32. set the division ra tio using the clock input source select bits (bits 5 to 3 in smr1 register: cs2 to cs0). table 14.5-3 baud rate (clock synchronous) cs2 cs1 cs0 clk synchronous calculation 0 0 0 2 mbps ( /div) / 1 0 0 1 1 mbps ( /div) / 2 0 1 0 500 kbps ( /div) / 4 0 1 1 250 kbps ( /div) / 8 1 0 0 125 kbps ( /div) / 16 1 0 1 62.5 kbps ( /div) / 32 : machine clock frequency div: division ratio based on communication prescaler .com .com .com .com 4 .com u datasheet
405 chapter 14 uart1 14.5.2 baud rate by internal timer (16-bit reload timer) the setting when selecting the internal clock supplied from the 16-bit reload timer 1 as the clock input source of the uart1 and t he baud rate calculati on are shown below. baud rate by internal time r (16-bit reload timer output) the baud rate based on the internal timer (16-bit reload timer output) is set by setting the clock input source select bits (smr1 register bit 5 to 3: cs2 to cs0) to "110 b ". any baud rate can be set by selecting the division ratio of the count clock and the re load value of the 16-bi t reload timer freely. figure 14.5-3 shows the baud rate selector based on the internal timer. if the internal timer (16-bit reload timer) is select ed as a clock input source (smr1 register bit 5 to 3: cs2 to cs0), the 16-bit reload timer output pin (tot) is connected internally and does not need to be connected extern ally to the external clock input pin (sck). the 16-bit reload timer output pin (tot) can be used as a general-purpose i/o port when it is not being used in other way. figure 14.5-3 baud rate selector by internal timer (16-bit reload timer output) calculation expression for baud rate : machine clock frequency n: division ratio based on communicati on prescaler for 16-bit reload timer (2 1 , 2 3 , 2 5 ) n: reload value for 16-bit reload timer (0 to 65,535) clock selector smr1: cs2 to cs0 = "110 b " (clock input source select bits) 1/1 [clock synchronous] 1/16 [asynchronous] baud rate 16-bit reload timer output (the frequency is specified by the count-clock division ratio and the reload value) smr1: md1, md0 (operation mode select bits) bps 16 2 (n+1) / n asynchronous baud rate = clock synchronous = bps 2 (n+1) / n .com .com .com .com 4 .com u datasheet
406 chapter 14 uart1 example of setting baud rates and reload register setting values (machine clock frequency: 7.3728 mhz) table 14.5-4 baud rate and reload value baud rate (bps) reload value clock asynchronous (start-stop synchronization) clock synchronous n = 2 1 (machine clock 2-divided) n = 2 3 (machine clock 8-divided) n = 2 1 (machine clock 2-divided) n = 2 3 (machine clock 8-divided) 38,400 2 ? 47 11 19,200 5 ? 95 23 9,600 11 2 191 47 4,800 23 5 383 95 2,400 47 11 767 191 1,200 95 23 1,535 383 600 191 47 3,071 767 300 383 95 6,143 1,535 n: division ratio based on communication prescaler for 16-bit reload timer ? : setting disabled .com .com .com .com 4 .com u datasheet
407 chapter 14 uart1 14.5.3 baud rate by external clock this section explains the setting when select ing the external clock as the transmit/ receive clock of the uart1. baud rate by external clock to select a baud rate by th e external clock input , the following settings are essential: set the clock input source select bits in the serial mode register (smr1 register bit 5 to 3: cs2 to cs0) to "111 b ". set the sck1 pin as the input port in the port direction register (ddr). set the serial clock i/o enable b it (smr1 register bit 1: scke) to 0. set the baud rate on the basis of the external clock input from the sck1 pin. since the internal division ratio is fixed, the external input clock must be changed in changing the baud rate. figure 14.5-4 baud rate selector by external clock expressions to obtain baud rate asynchronous baud rate = f/16 bps clock synchronous baud rate = f bps f: external clock frequency (2 mhz max.) clock selector smr1: cs2 to cs0 = "111 b " (clock input source select bits) 1/1 [clock synchronous] 1/16 [asynchronous] baud rate sck1 smr1: md1, md0 (operation mode select bits) pin .com .com .com .com 4 .com u datasheet
408 chapter 14 uart1 14.6 explanation of operation of uart1 the uart1 has master/slave type connection communicati on function (operation mode 1: asynchronous multiprocessor mode) in addition to bidirectional serial communication function ( operation modes 0 and 2: asynchronous normal mode and clock synchronous mode). operation of uart1 operation mode the uart1 has three types of operation modes, th ey can set the inter-cpu connection mode or data communication mode. table 14.6-1 shows operation mode of uart1. inter-cpu connection mode either 1-to-1 connection or master/slave type conn ection can be selected fo r the inter-cpu connection mode. in both cases, the data length, parity, synchrono us or asynchronous mode, etc., must be the same for all cpus. the operation modes are selected as follows. for the 1-to-1 connection, the same operation mode (either operation mode 0 or 2: normal mode, clock synchronous mode) must be adopted for the two cpus. for the asynchronous mode, select operation mode 1: asynchronous multiprocessor mode (smr1 register bit 7, 6: md1, md0 = "00 b "): for the synchronous mode select operation mode 2: clock synchronous mode (smr1 register bit 7, 6: md1, md0 = "10 b "). for the master/slave type connection, operation mode 1: asynchronous multiprocessor mode (smr1 register bit 7, 6: md1, md0 = "01 b " is set; select operation mode 1 (asynchronous multiprocessor mode) and use it as the master. for this connect ion, select no parity and 8-bit data length. table 14.6-1 operation mode of uart 1 operation mode data length synchronous/ asynchronous length of stop bit no parity with parity 0 normal mode 7 bits or 8 bits asynchronous 1 bit or 2 bits *2 1 multiprocessor mode 8 + 1 *1 ? asynchronous 2 clock synchronous mode 8 ? synchronous none ? : setting disabled *1: +1 is the address/data select bit (scr1 register bit 11: a/d) used for controlling communications. *2: during reception , only one bit can be de tected as the stop bit. note: the uart1 operation mode 1 (asynchronous multiprocessor mode) is only used as the master in the master/slave type connection. .com .com .com .com 4 .com u datasheet
409 chapter 14 uart1 synchronous/asynchronous for the operation modes, either the asynchronous mode (start-stop synchronization) or the clock- synchronous mode can be selected. signal mode the uart1 can only handle the nrz (non return to zero) data format. start of transmission/reception transmission starts when the transmission enable bit of the serial control register (scr1 register bit 8: txe) is set to 1. reception starts when the reception en able bit of the serial control regi ster (scr1 register bit 9: rxe) is set to 1. stop of transmission/reception transmission stops when the transmission enable bit of the serial control regist er (scr1 register bit 8: txe) is set to 0. reception stops when the reception en able bit of the serial control register (scr1 re gister bit 9: rxe) is set to 0. stop during transmission/reception when reception is disabled duri ng receiving (during data input to reception shift register) (scr1 register bit 9: rxe = 0), it stop s after reception of the frame being received is completed and the receive data is stored to the serial input data register 1 (sidr1). when transmission is disabled du ring transmission (during data output from the transmission shift register) (scr1 register bit 8: txe = 0), it stops afte r transmission of one frame to the transmission shift register from the serial output data register 1 (sodr1) is completed. .com .com .com .com 4 .com u datasheet
410 chapter 14 uart1 14.6.1 operation in asynchronous mode (operation mode 0 or 1) when the uart 1 is used in operation mode 0 (asy nchronous normal mode) or operation mode 1 (asynchr onous multiprocessor mode), the asynchronous transfer mode is selected. operation in asynchronous mode format of transmit/receive data transmission and reception always st art with the start bit (low leve l); transmission and reception are performed at the specified data bit length on lsb first basis and end with the stop bit (high level). in operation mode 0 (asynchronous normal mode), the data length can be set to 7 or 8 bits. use of the parity bit can be specified. in operation mode 1 (asynchronous multiprocessor mode), the data length is fixed to 8 bits. there is no parity bit. the address/data bit (scr1 register bit 11: a/d) is added to bit 9. figure 14.6-1 shows the tran smit/receive data format in the asynchronous mode. .com .com .com .com 4 .com u datasheet
411 chapter 14 uart1 figure 14.6-1 format of transmit/receive data (operation mode 0 or 1) transmission transmit data is written to the serial output data register 1 (sodr1) with the transmit data write flag bit (ssr1 register bit 11: tdre) set to 1. transmission starts when transmit data is written an d the transmit enable bit of the serial control register (scr1 register bit 8: txe) is set to 1. the transmit data write flag bit (ssr1 register bi t 11: tdre) is cleared to 0 temporarily when transmit data is written to sodr1. the transmit data write flag bit (ssr1 register bi t 11: tdre) is set to 1 again once the transmit data is written to the send shift register from the serial output data register 1 (sodr1). when the transmit interrupt enable bit (ssr1 register bit 8: tie) is set to 1, a send interrupt request is issued once the send data write flag bit (ssr1 regi ster bit 11: tdre) is set to 1. the succeeding send data can be written to the serial output data register 1 (sodr1) at interrupt processing. [operation mode 0] st : start bit sp : stop bit p : parity bit a/d : address/data bit [operation mode 1] d8 sp st st st st st st st st st st d0 d1 d2 d3 d5 d4 d7 d8 d0 d1 d2 d3 d5 d4 d7 sp sp d8 p d0 d1 d2 d3 d5 d4 d7 sp d8 p d0 d1 d2 d3 d5 d4 d7 sp sp d8 a/d d0 d1 d2 d3 d5 d4 d7 sp d8 a/d d0 d1 d2 d3 d5 d4 d7 sp sp sp d0 d1 d2 d3 d5 d4 d7 sp d0 d1 d2 d3 d5 d4 d7 sp p d0 d1 d2 d3 d5 d4 d7 sp sp p d0 d1 d2 d3 d5 d4 d7 sp data 7 bits data 8 bits p not provided p provided p not provided p provided data 8 bits .com .com .com .com 4 .com u datasheet
412 chapter 14 uart1 reception when reception is enabled (scr1 register bit 9: rxe = 1), receiving is always performed. when the start bit of receive data is detected, the se rial input data register 1 (sidr1) receives one frame of data and stores data to the serial input data re gister 1 (sidr1) according to the data format specified in the serial control register 1 (scr1). at completion of receiving one frame of data, the r eceive data load flag b it (ssr1 register bit 12: rdrf) is set to 1. when the status of the error flag of the serial status register 1 (ssr1) is checked to find normal reception at the completion of one frame of data, read the receive data from the serial input data register 1 (sidr1). when a receive error occurs, perform error processing. the receive data load flag bit (ssr1 register bit 12 : rdrf) is cleared to 0 when receive data is read. .com .com .com .com 4 .com u datasheet
413 chapter 14 uart1 detecting the start bit implement the following settings to detect the start bit: set the communication line level to h (attach the mark level) before the communication period. specify reception permission (r xe = h) while the communicatio n line level is h (mark level). do not specify reception permission (rxe = h) for periods other than the communication period (without mark level). otherwise, data is not received correctly. after the stop bit is detected (t he rdrf flag is set to 1), specify reception inhibition (rxe = l) while the communication line level is h (mark level). figure 14.6-2 example of normal operation note that specifying reception perm ission at the timing shown below obstructs the correct recognition of the input data (sin) by the microcontroller. example of operation if recepti on permission (rxe = h) is spec ified while the communication line level is l. figure 14.6-3 example of abnormal operation stop bit during transmission, one bit or two bits can be select ed. however, the receive side always detects only the first bit. st d0 d1 d2 d3 d4 d5 d6 d7 sp st d0 d1 d2 d3 d4 d5 d6 d7 sp non-communication period non-communication period communication period mark level start bit data stop bit sin (sending 01010101 b ) rxe receive clock sampling clock recognition by the microcontroller (receiving 01010101 b ) receive clock (8 pulse) generating sampling clocks by dividing the receive clock by 16 st d0 d1 d2 d3 d4 d5 d6 d7 sp st recognition d0 d1 d2 d3 d4 d5 d6 d7 sp sin rxe pe,ore,fre non-communication period non-communication period communication period mark level start bit data stop bit (sending 01010101 b ) receive clock sampling clock recognition by the microcontroller (receiving 10101010 b ) occurrence of a reception error .com .com .com .com 4 .com u datasheet
414 chapter 14 uart1 error detection in operation mode 0 (asynchronous normal mode), par ity, overrun, and frame errors can be detected. in operation mode 1 (asynchronous multiprocessor mode ), overrun and frame errors can be detected, but parity errors cannot be detected. parity bit a parity bit can be set only in operation mode 0 (asynchronous normal mode). the parity addition enable bit (scr1 register bit 15: pen) is used to specify whet her there is parity or not, and the parity select bit (scr1 register bit 14: p) is used to select odd or even parity. there is no parity bit in operation modes 1 (asynchronous multiprocessor mode). the transmit/receive data when the parity bit enabled are shown in figure 14.6-4. figure 14.6-4 transmit/receive data when parity bit enabled when receiving 101 01 01 01 10 0 1 when transmitting 10110 0 0 when transmitting sin1 sot1 sot1 parity error at reception with even parity (scr1: pen = 1, p = 0) transmission with even parity (scr1: pen = 1, p = 0) transmission with odd parity (scr1: pen = 1, p = 1) 10110 0 1 st : start bit sp : stop bit note : parity bit cannot be set in operation mode 1. data st sp st sp st sp parity .com .com .com .com 4 .com u datasheet
415 chapter 14 uart1 14.6.2 operation in clock synchronous mode (operation mode 2) when the uart1 is used in oper ation mode 2, the transf er mode is clock synchronous. operation in clock synchr onous mode (ope ration mode 2) format of transmit/receive data in the clock synchronous mode, 8-bit data is transmitt ed/received on lsb-first, and the start and stop bits are not added. figure 14.6-5 shows the transm it/receive data format for the clock synchronous mode. figure 14.6-5 format of transmit/receive data (operation mode 2) write transmit data outputting serial clock for transmitting 10 011 001 mark level sck1 output txe sot1 (lsb) (msb) transmit data read receive data inputting serial clock for receiving 10 011 001 mark level sck1 input rxe sin1 (lsb) (msb) receive data .com .com .com .com 4 .com u datasheet
416 chapter 14 uart1 clock supply in the clock synchronous mode, count of clocks equal to the transmit and receive bits count must be supplied. when the internal clock (dedicated baud rate genera tor or internal timer) ha s already selected (smr1 register bit 5 to 3: cs2 to cs0 = "000 b " to "101 b " or "110 b ") and data is transmitted, the synchronous clock for data reception is generated automatically. when the external clock has already selected (smr1 register bit 5 to 3: cs2 to cs0 = "111 b "), the clock for exact one byte must be supplied from outside after ensuring that data is present (ssr1 register bit 11: tdre = 0) in the serial output data register 1 (sodr1). also, before and after transmitting, always return to the mark level (high level). error detection only overrun errors can be detected; pari ty and framing errors cannot be detected. setting of register table 14.6-2 shows the setting of the control register in transmitting serial data from the transmitting end to the receiving end using the clock s ynchronous mode (o peration mode 2). table 14.6-2 setting of control register register name bit name setting transmit end (output serial clock) receive end (input serial clock) serial mode register 1 (smr1) md1, md0 set clock synchronous mode (md1, md0 = "10 b "). cs2, cs1, cs0 set clock input source. dedicated baud rate generator (cs2 to cs0 = "000 b " to "101 b ") internal timer (cs2 to cs0 = "110 b ") set clock input source. external clock (cs2 to cs0 = "111 b ") scke set serial clock output (scke = 1). set serial clock input (scke = 0). soe set serial data output pin (soe = 1). set general-purpose i/o port (soe = 0). serial control register 1 (scr1) pen do not add parity bit (pen = 0). cl 8-bit data length (cl = 1) rec initialize error flag (rec = 0). txe enable transmitting (txe = 1). disable transmitting (txe = 0). rxe disable receiving (rxe = 0). enable receiving (rxe = 1). serial status register 1 (ssr1) tie enable transmitting interrupt (tie = 1) disable transmitting interrupt (tie = 0) rie disable receiving interrupt (rie = 0) . enable receiving interrupt (rie = 1). .com .com .com .com 4 .com u datasheet
417 chapter 14 uart1 starting communications when send data is written to the serial output data register 1 (sodr1), comm unication is started. when starting communication only in receiving, it is always necessary to write dummy send data to the serial output data register 1 (sodr1). terminating communications after transmitting and receivin g of one frame of data, the receive data load flag bit (ssr1 register bit 12: rdrf) is set to 1. when data is received, check the overrun error flag bit (ssr 1 register bit 14: ore) to ensure that the communicat ion has performed normally. .com .com .com .com 4 .com u datasheet
418 chapter 14 uart1 14.6.3 bidirectional communication function (operation modes 0 and 2) in operation modes 0 and 2 (asynchronous normal mode , clock synchronous mode), normal serial bidirectiona l communications using 1-to-1 connection can be performed. for operation mode 0 (async hronous normal mode), t he asynchronous mode is used; for operation mode 2 (clock synchronous mode ), the clock sync hronous mode is used. bidirectional comm unication function to operate the uart1 in the operation mode 0, 2 (asynchronous normal mode, clock synchronous mode), shown in figure 14.6-6 is required. figure 14.6-6 setting of operation modes 0, 2 (asynchronous normal mode and clock synchronous mode) for uart1 inter-cpu connect connect the two cpus as shown in figure 14.6-7. figure 14.6-7 example of bidirectional communication connect for uart1 bit1514131211109bit8bit7654321bit0 scr1, smr1 pen p sbl cl ad rec rxe txe md1 md0 cs2 cs1 cs0 reser ved scke soe operation mode 0 operation mode 2 0xx1 x x 0 0 0 1 0 0 0 0 ssr1, sidr1/sodr1 pe ore fre rdrf tdre ? rie tie setting of transmit data (at write) / retention of receive data (at read) operation mode 0 operation mode 2 xx ddr port direction register ? : unused bit : used bit x : undefined bit 1: set 1 0: set 0 set the bit to 0 corresponding to pin used as sin1 and sck1 input pins. sot1 sin1 sck1 sot sin sck cpu-1 cpu-2 output input .com .com .com .com 4 .com u datasheet
419 chapter 14 uart1 communication procedure communications start at any timing from the transmitting end when transmit data is provided. at the transmitting end, set transmit data in the serial output data register (sodr1) and set the transmitting enable bit in the serial control regi ster (scr1 register bit 8: txe) to 1 to start transmitting. figure 14.6-8 gives an example of transferring receive data to th e transmitting end to inform the transmitting end of normal reception. figure 14.6-8 flowchart for bidirectional communication start read and process receive data set the 1-byte data in sodr1 receive data presence receive data presence data transmission data transmission no no set the operation mode (0 or 2) (transmit end) start transmit 1-byte data set the operation mode (same as transmit end) (receive end) yes yes read and process receive data .com .com .com .com 4 .com u datasheet
420 chapter 14 uart1 14.6.4 master/slave type communication function (multiprocessor mode) operation mode 1 (asynchronous multipr ocessor mode) enables communications by the master/slave type connecti on of more than one cpu. only the master cpu functions. master/slave type communication function to operate the uart1 in operation mode 1 (asynchronous multiprocessor mode), the setting shown in figure 14.6-9 is required. figure 14.6-9 setting of operation mode 1 (asynchronous multiprocessor mode) for uart1 inter-cpu connect one master cpu and more than one slave cpu are connected to two common communication lines to compose the communication system. the uart1 can be used only as the master cpu. figure 14.6-10 example of master/slave type communication connect for uart1 bit1514131211109bit8bit7654321bit0 scr1, smr1 pen p sbl cl ad rec rxe txe md1 md0 cs2 cs1 cs0 rese rved scke soe 0x 1 0 01 00 ssr1, sidr1/sodr1 pe ore fre rdrf tdre ? rie tie setting of transmit data (at write) / retention of receive data (at read) x ddr port direction register ? : unused bit : used bit x : undefined bit 1: set 1 0: set 0 set the bit to 0 corresponding to pin used as sin1 and sck1 input pins. sot1 sin1 sot sin sot sin master cpu slave cpu #0 slave cpu #1 .com .com .com .com 4 .com u datasheet
421 chapter 14 uart1 function select at master/slave type communication, select the operation mode and data transfer type. since the parity check function cannot be used in operation mode 1 (asynchronous multiprocessor mode), set the parity add enable bit (scr1 register bit 15: pen) to 0. communication procedure communications start wh en the master cpu transmits address data. the address data is data with the a/d bit set to 1. the address/data select bit (scr1 register bit 11: a/d) is added to select the slave cpu th at the master cpu communicates with. when the program identifies address data and finds a match with the allocated address, each slave cp u starts communications with the master cpu. figure 14.6-11 shows the flowchart for master/slave type communications. table 14.6-3 select of master/slave type communication function operation mode data parity synchronous system stop bit master cpu slave cpu address transmit/ receive operation mode 1 ? a/d = 1 + 8-bit address not provided asynchronous 1 bit or 2 bits data transmit/ receive a/d = 0 + 8-bit data .com .com .com .com 4 .com u datasheet
422 chapter 14 uart1 figure 14.6-11 flowchart for master/slave type communications start set 0 to a/d reception enabled set 1-byte data (address data) that selects the slave cpu to d0 to d7 to transmit (a/d = 1) communicate with slave cpu reception disabled end select the operation mode 1 (asynchronous multiprocessor mode) (master cpu) communication ended? yes no communicate with other slave cpu yes no .com .com .com .com 4 .com u datasheet
423 chapter 14 uart1 14.7 precautions when using uart1 use of the uart1 requir es the following cautions. precautions when using uart1 enabling sending and receiving the send enable bit (scr1 register bit 8: txe) and receive enable b it (scr1 register bit 9: rxe) are provided for sending and receiving. in the initial state after reset, both sending and recei ving are disabled (scr1 regi ster bit 8: txe = 0, bit 9: rxe = 0). therefore, it is n ecessary to enable sending and receiving. sending and receiving are disabled to stop (scr1 register bit 8: txe = 0, bit 9: rxe = 0). setting operation mode set the operation mode after disabling sending and recei ving (scr1 register bit 8: txe = 0, bit 9: rxe = 0). when the operati on mode is changed during sending and recei ving, the sent and received data is not assured. clock synchronous mode operation mode 2 (clock synchronous mode) is set as the clock synchronous mode. send and receive data do not have the start and stop bits. timing of enabling send interrupt the initial value after reset of the send data write enable flag bit (ssr1 register bit 11: tdre) is set at 1 (no send data, send data write enabled). therefore, the se nd interrupt is enabled (ssr1 register bit 8: tie = 1) and a send interrupt request is issued simultaneo usly. always prepare send data and enable a send interrupt (ssr1 register bit 8: tie = 1). .com .com .com .com 4 .com u datasheet
424 chapter 14 uart1 14.8 program example for uart1 this section gives a program example for the uart1. program example for uart1 processing the bidirectional communication function (normal m ode) of the uart1 is used to perform serial transmission/reception. set operation mode 0, asynchronous mode (normal) , 8-bit data length, 2-bit stop bit length, and no parity. use the p40/sin1 and p42/so t1 pins for communications. use the dedicated baud rate generator to set the baud rate to approximately 9600 bps. transmit the character 13 h from the sot1 pin and receive it at an interrupt. assume the machine clock ( ) 16 mhz. .com .com .com .com 4 .com u datasheet
425 chapter 14 uart1 coding example icr13 equ 0000bdh ; uart transmit/receive interrupt control register ddr1 equ 000011h ; port 1 data direction register cdcr1 equ 00001bh ; communication prescaler register 1 smr1 equ 000024h ; mode control register 1 scr1 equ 000025h ; control register 1 sidr1 equ 00002 6 h ; input data register 1 sodr1 equ 00002 6 h ; output data register 1 ssr1 equ 000027h ; status register 1 rec equ scr1:2 ; receive error flag clear bit ;-----main program--------------------------------------------------------------- code cseg abs=0ffh start: ; : ; assume stack pointer (sp) already reset and ccr,#0bfh ; disable interrupt mov i:icr13,#00h ; interrupt level 0 (highest priority) mov i:ddr1,#00000000b ; set sin1 as input pin. mov i:cdcr1,#0 8 0h ; enable communication prescaler mov i:smr1,#00010001b ; operation mode 0 (asynchronous) ; use dedicated baud rate generator (9 6 15 bps) ; disable clock pulse output and enable data output mov i:scr1,#00010011b ; without n parity. 2-bit stop bit ; clear 8 -bit data bit and receive error flag ; enable transmitting/receiving mov i:ssr1,#00000010b ; disable transmit interrupt and enable receive ; interrupt mov i:sodr1,#13h ; write send data mov ilm,#07h ; set ilm of ps to level 7 or ccr,#40h ; enable interrupt loop: mov a,#00h ; infinite loop mov a,#01h bra loop ;-----interruption program------------------------------------------------------- wari: mov a,sidr1 ; read receive data clrb i:rec ; clear receive interrupt request flag ; : ; processing by user ; : reti ; return from interrupt code ends ;-----vector setting------------------------------------------------------------- vect cseg abs=0ffh org 0ff 68 h ; set interrupt #37 (25h) vector dsl wari org 0ffdch ; set reset vector dsl start db 00h ; set single-chip mode vect ends .com .com .com .com 4 .com u datasheet
426 chapter 14 uart1 .com .com .com .com 4 .com u datasheet
427 chapter 15 can controller this chapter explains the f unctions and o perations of the can controller. 15.1 overview of can controller 15.2 block diagram of can controller 15.3 configuration of can controller 15.4 interrupts of can controller 15.5 explanation of operation of can controller 15.6 precautions when using can controller 15.7 program example of can controller .com .com .com .com 4 .com u datasheet
428 chapter 15 can controller 15.1 overview of can controller the can (controller ar ea network) is a serial communi cation protocol conformed to can ver. 2.0a and ver. 2.0b. transmitti ng and receiving can be performed in the standard frame format and th e extended frame format. overview of can controller the can controller format conforms to can ver. 2.0a and ver. 2.0b. transmitting and receiving can be performed in the standard fram e format and the extended frame format. data frames can be transmitted auto matically by remote frames receiving. the baud rate ranges from 10 kpbs to 1 mbps (at 16-mhz machine clock frequency). the can controller equips eight transmit/receive message buffers. the standard frame format provides transmitting and receiving with 11-bit id and the extended frame format 29-bit id. message data can be set from 0 byte to 8 bytes. message buffer configuration can be performed at a multilevel. the can controller has two acceptance mask register s. these registers can set masks independently for the receive message id. the two acceptance mask registers can receive in th e format of standard fr ame and extended frame. four masks can be set at all bit comparison and ma sking, and partially at acceptance mask registers 0 and 1. table 15.1-1 data transfer baud rate machine clock baud rate 16 mhz 1 mbps 12 mhz 1 mbps 8 mhz 1 mbps 4 mhz 500 kbps 2 mhz 250 kbps .com .com .com .com 4 .com u datasheet
429 chapter 15 can controller 15.2 block diagram of can controller the can controller consist s of two types of registers; one controls the can controller and the other controls each message buffer. block diagram of can controller figure 15.2-1 block di agram of can controller tx f 2 mc-16lx bus cpu operation clock prescaler (1 to 64-divided clock) bit timing generator operation clock (tq) sync segment time segment 1 time segment 2 node status transition interrupt generator node status transition interrupt signal transmit buffer clear transmit buffer arbitration lost transmit buffer sets and clears transmit buffer sets receive buffer sets and clears receive buffer and transmit buffer sets receive buffer id select transmission complete interrupt signal reception complete interrupt signal crc generator ack generator transmission complete interrupt generator acceptance filter receive buffer determining circuit reception complete interrupt generator ram address generator transmit dlc receive dlc stuff error receive buffer receive buffer, transmit buffer, receive dlc, transmit dlc, id select arbitration lost arbitration check acknowledgement error check ack error form error bit error check form error check bit error crc error transmit dlc receive dlc id select data counter error frame generator output driver input latch pin pin overload frame generator acceptance filter controller bit error, stuff error, crc error, frame error, ack error transmission shift register reception shift register crc generator/error check destuffing/stuffing error check stuffing transmit buffer determining circuit transmit/receive sequencer error controller bus state determining circuit idle, interrupt, suspend, transmit, receive, error, overload btr psc ts1 ts2 rsj toe ts rs halt nie nt ns1,0 csr rtec bvalr treqr tcanr trtrr rfwtr tcr tier rcr rier rrtrr rovrr amsr amr0 amr1 0 1 leir idr0 to 7 dlcr0 to 7 dtr0 to 7 ram rx ider .com .com .com .com 4 .com u datasheet
430 chapter 15 can controller the pin names in the block diagram are as follows: tx pin: p43/tx rx pin: p44/rx bit timing register (btr) this register sets the division ratio at which can bit timing is generated. control status register (csr) this register controls the operation of the can controller. it indicates the state of transmitting/receiving and the can bus, controls interrupts, and controls the bus halt and indicates its state. receive/transmit error counter register (rtec) this register indicates the number of times transmit and receive errors have occurred. it counts up when an error occurs in transmitt ing and receiving messages and counts dow n when transmitting and receiving are performed normally. message buffer validating register (bvalr) this register enables or disables a specified message buffer, and also indicates th e enabled/disabled status. ide register (ider) this register sets the frame format of each message buffer. it sets th e standard frame fo rmat or extended frame format. transmit request register (treqr) this register sets a transmit request to each message buffer. transmit cancel register (tcanr) this register cancels transmit requests held in each message buffer. transmit rtr register (trtrr) this register selects a frame format transmitted to each message buffer. it selects the data frame or remote frame. remote frame receive waiting register (rfwtr) this register sets the condition for transmitting start when a transmit request of the data frame is set. transmit complete register (tcr) the bit is set which is corresponding to the number of the message buffer that completes message transmitting. .com .com .com .com 4 .com u datasheet
431 chapter 15 can controller transmit complete interrupt enable register (tier) this register controls the generation of an in terrupt request when each message buffer completes transmitting. when an interrupt is enabled, an interrupt request is generated when transmitting is completed. receive complete register (rcr) this register sets the bit corresponding to the number of the message buffe r that completes receiving message. receive complete interrupt enable register (rier) this register controls output of an interrupt request when each me ssage buffer completes receiving. if output of an interrupt request is enabled, an inte rrupt request is output at completion of receiving. receive rtr register (rrtrr) when a remote frame is stored in a message buffer, the bit correspo nding to the number of the message buffer is set. receive overrun register (rovrr) this register sets the bit corresponding to the num ber of the message buffer that overruns when the message is received. acceptance mask select register (amsr) this register sets the meth od for masking the receive me ssage for each message buffer. acceptance mask regist ers (amr0 and amr1) these registers set a mask with the id for filtering the message to be received. last event indication register (leir) this register indicates the operating state that last occurred. it i ndicates that either node status transition, transmitting completion, or receiving completion occurred. prescaler the prescaler generates a bit timing clock at a frequency of 1/1 to 1/64 of the system clock. it sets the operation clock (tq). bit timing generator this generator detects a bit timing clock signal to generate a sync segment and time segments 1 and 2. node status transition interrupt generator this generates a node status transition interr upt signal when the node status transits. .com .com .com .com 4 .com u datasheet
432 chapter 15 can controller bus state identification circuit this circuit identifies the can bus state from the bus halt bit (csr: halt) and the signal from the error frame generator. acceptance filter this filter compares the receive message id with th e acceptance code to select the message to be received. transmit message buffers/receive message buffers there are 8 message buffers to store the message to be transmitted and received. crc generator/ack generator this circuit generates a crc field or an ack field when a data frame or remo te frame is transmitted. .com .com .com .com 4 .com u datasheet
433 chapter 15 can controller 15.3 configuration of can controller this section explains the pins and, related registers, interrupt factors of the can controller. pins of can controller block diagram for pi ns of can controller see "chapter 4 i/o port" for details of the block diagram of pins. table 15.3-1 pins of can controller pin name pin function setting of pin used in can controller tx transmit output pin general-purpose i/o port specify tx pin as transmit output pin (when toe bit in csr register set to 1) rx receive input pin general-purpose i/o port specify rx pin as receive input pin (when bit 4 in ddr4 register set to 0) .com .com .com .com 4 .com u datasheet
434 chapter 15 can controller can controller registers figure 15.3-1, figure 15.3-2 and figure 15.3-3 list the registers of the can controller. figure 15.3-1 registers of can controller (control registers) bit 15 bit 7 bit 0 bit 8 bit 15 bit 7 bit 0 bit 8 reserved area* reserved area* reserved area* reserved area* reserved area* reserved area* reserved area* reserved area* reserved area* reserved area* reserved area* reserved area* reserved area* *: reserved area cannot be used because address is used in the system. reserved area* 00000000 b 00000000 b 00000000 b 00000000 b 00000000 b 00000000 b 00000000 b 00000000 b bvalr (message buffer enable register) treqr (transmission request register) tcanr (transmission cancel register) tcr (transmission complete register) rcr (reception complete register) rrtrr (reception rtr register) rovrr (reception overrun register) rier (reception complete interrupt enable register) csr (control status register) rtec (receive/transmit error counter) amsr (acceptance mask select register) btr (bit timing register) amr1 (acceptance mask register 1) amr0 (acceptance mask register 0) can controller control register reset value xxxxxxxx b xxxxxxxx b xxxxxxxx b xxxxxxxx b reset value 00xxx000 b 000xx000 b 00000000 b x1111111 b xxxxxxxx b 00000000 b xxxxxxxx b 00000000 b xxxxxxxx b xxxxxxxx b xxxxxxxx b xxxxxxxx b xxxxxxxx b 0 xxxx0 0 1 b 00000000 b 11111111 b xxxxxxxx b leir (last event indicate register) ider (ide register) trtrr(transmission rtr register) rfwtr (remote frame receive waiting register) tier (transmission complete interrupt enable register) .com .com .com .com 4 .com u datasheet
435 chapter 15 can controller figure 15.3-2 re gisters of can controller (id register and dlc register) bit 7 bit 0 dlc0 (dlc register 0) dlc1 (dlc register 1) dlc2 (dlc register 2) dlc3 (dlc register 3) dlc4 (dlc register 4) dlc5 (dlc register 5) dlc6 (dlc register 6) dlc7 (dlc register 7) message buffer (dlc register) *: reserved area cannot be used because address is used in the system. xxxxxxxx b xxxxxxxx b xxxxxxxx b xxxxxxxx b xxxxxxxx b xxxxxxxx b xxxxxxxx b xxxxxxxx b reset value bit 15 bit 7 bit 0 bit 8 ram (general-purpose ram) (16 bytes) idr0 (id register 0) idr1 (id register 1) idr2 (id register 2) idr3 (id register 3) idr4 (id register 4) idr5 (id register 5) idr6 (id register 6) idr7 (id register 7) message buffer (id register) reset value xxxxxxxx b ~ ~ xxxxxxxx b xxxxxxxx b xxxxxxxx b xxxxxxxx b xxxxxxxx b xxxxxxxx b xxxxxxxx b xxxxxxxx b xxxxxxxx b xxxxxxxx b xxxxxxxx b xxxxxxxx b xxxxxxxx b xxxxxxxx b xxxxxxxx b xxxxxxxx b xxxxxxxx b xxxxxxxx b xxxxxxxx b xxxxxxxx b xxxxxxxx b xxxxxxxx b xxxxxxxx b xxxxxxxx b xxxxxxxx b xxxxxxxx b xxxxxxxx b xxxxxxxx b xxxxxxxx b xxxxxxxx b xxxxxxxx b xxxxxxxx b xxxxxxxx b bit 15 bit 8 reserved area* reserved area* reserved area* reserved area* reserved area* reserved area* reserved area* reserved area* .com .com .com .com 4 .com u datasheet
436 chapter 15 can controller figure 15.3-3 regi sters of can controll er (dtr register) generation of interrupt request by can controller the can controller has a transmit complete interrupt, receive complete interrupt, and node status interrupt. each interrupt request is generated as follows: when a transmit complete interrupt is enabled for th e message buffer (x) (tier: tiex = 1), the tcx bit in the transmit complete register is set to 1 and a transmit complete interrupt request is generated after a completion of message transmitting. when a receive complete interrupt is enabled for th e message buffer (x) (rier: riex = 1), the rcx bit in the receive complete register is set to 1 and a r eceive complete interrupt request is generated after a completion of message receiving. when a node status transition interrupt is enabled (csr: nie = 1), the nt bit in the can status register is set to 1 and a node status transition interrupt re quest is generated after the node status transits. bit 15 bit 7 bit 0 bit 8 dtr0 (data register 0) (8 bytes) dtr1 (data register 1) (8 bytes) dtr2 (data register 2) (8 bytes) dtr3 (data register 3) (8 bytes) dtr4 (data register 4) (8 bytes) dtr5 (data register 5) (8 bytes) dtr6 (data register 6) (8 bytes) dtr7 (data register 7) (8 bytes) reserved area* (128 bytes) message buffer (dtr register) *: reserved area cannot be used because address is used in the system. reset value xxxxxxxx b xxxxxxxx b xxxxxxxx b xxxxxxxx b xxxxxxxx b xxxxxxxx b xxxxxxxx b xxxxxxxx b xxxxxxxx b xxxxxxxx b xxxxxxxx b xxxxxxxx b xxxxxxxx b xxxxxxxx b xxxxxxxx b xxxxxxxx b ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ .com .com .com .com 4 .com u datasheet
437 chapter 15 can controller 15.3.1 control status register (high) (csr: h) the control status register (csr) controls operation of the can controller. the control status register (high) (csr: h) transmits and receives the message and indicates the node status. control status regist er (high) (csr: h) figure 15.3-4 control status register (high) (csr: h) note: it is prohibited to execute a bit operation (read-mod ify-write) instruction on the lower 8 bits of control status register (csr). only in the case of halt bits unchanged, use any bit operation instructions without problems (initialization of the macro instructions, etc.). reset value 00xxx000 b 12 13 11 10 9 15 14 8 r r r/w ? ? ? r rs receive status bit message is not received message is being received bit 14 0 1 ts transmit status bit message is not transmitted message is being transmitted bit 15 0 1 node status bits ns1 error active warning (error active) error passive bus off bit 9 0 0 1 1 ns0 bit 8 0 1 0 1 nt node status transition flag no node status transition node status transition bit 10 0 1 r r/w : read/write r : read only x : undefined ? : unused : reset value .com .com .com .com 4 .com u datasheet
438 chapter 15 can controller table 15.3-2 functions of control status register (high) (csr: h) bit name function bit 8 bit 9 ns1, ns0: node status bits the combination of the ns 1 and ns0 bits indicates the current node status. 00 b : error active 01 b : warning (error active) 10 b : error passive 11 b : bus off note: warning is included in error active in the can specifications as a node status. bit 10 nt: node status transition flag bit this bit indicates that the node status transits. when node status transits: bit set to 1 1. error active (00 b ) --> warning (01 b ) 2. warning (01 b ) --> error passive (10 b ) 3. error passive (10 b ) --> bus off (11 b ) 4. bus off (11 b ) --> error active (00 b ) (the parenthesized values are those for the ns1 and ns0 bits.) when set to 0: clears this bit. when set to 1: disables bit setting read using read modify write instructions: 1 always read bit 11 to bit 13 unused bits read: value not fixed write: no effect bit 14 rs: receive status bit this bit indicates whether the message is being received. message being received: bit set to 1 for example, if the message is on the bus, even during message transmitting, this bit is set to 1 rega rdless of whether the receive message passes the acceptance filter. error frame or overload frame on bus: bit set to 0 when the rs bit is 0, the bus halt state (halt = 1), bus intermission state and bus idle state are also included. bit 15 ts: transmit status bit this bit indicates whether the message is being transmitted. message being transmitted: bit set to 1 error frame or overload frame being transmitted: bit set to 0 .com .com .com .com 4 .com u datasheet
439 chapter 15 can controller 15.3.2 control status register (low) (csr: l) the control status register (csr) controls operation of the can controller. the control status register (low) (csr: l) enables and disab les transmit interr upt and node status transition interrupt, controls bus halt and indicates the node status. control status regist er (low) (csr: l) figure 15.3-5 control status register (low) (csr: l) note: it is prohibited to execute a bit operation (read-mod ify-write) instruction on the lower 8 bits of control status register (csr). only in the case of halt bits unchanged, use any bit operation instructions without problems (initialization of the macro instructions, etc.). reset value 0xxxx001 b 4 5321 7 6 0 r/w w r/w ? ? ? r/w bit 7 bit 1 ? r/w : read/write w : write only x : undefined ? : unused : reset value always set "0" nie 0 1 node status transition interrupt output enable bit interrupt output disable by node status transition interrupt output enable by node status transition toe 0 1 transmit output enable bit used as general-purpose i/o port used as transmit pin tx halt 0 1 bus operation stop bit cancels bus operation stop (bus operation not in stop state) stops bus operation (bus operation in stop state) bit 0 reserved 0 reserved bit bit 2 .com .com .com .com 4 .com u datasheet
440 chapter 15 can controller table 15.3-3 functions of control status register (low) (csr: l) (1/2) bit name function bit 0 halt: bus halt bit this bit controls the bus halt. the halt state of the bus can be checked by reading this bit. writing to this bit 0: cancels bus operation stop 1: sets bus operation stop reading this bit 0: bus operation not in stop state 1: bus operation in stop state note: when write 0 to this bit during the node status is bus off, ensure that 1 is written to this bit. example program: switch ( io_canct0.csr.bit.ns ) { case 0 : /* error active */ break; case 1 : /* warning */ break; case 2 : /* error passive */ break; default : /* bus off */ for ( i=0; ( i <= 500 ) && ( io_canct0.csr.bit. halt == 0); i++); io_canct0.csr.word = 0x0084; /* halt = 0 */ break; } * : the variable "i" is used for fail-safe. [conditions for canceling bus halt] the state in which the bus is halted by a hardware reset or by writing 1 to the halt bit is cancelled after 0 is wr itten to the halt bit and an 11-bit high level (receive) is inpu t continuously to the receive input pin (rx). the state in the bus off is cancelled after 0 is written to the halt bit and an 11-bit high level (receive) is input continuously 128 times to the receive input pin (rx). the values of the transm it and receive er ror counters are both returned to 0 and the node status transits to error active. when write 0 to halt bit during the node status is bus off, ensure that 1 is written to this bit. [state in which bus halted] transmitting and receivi ng are not performed. a high level (receive) is output to the transmit ou tput pin (tx). values of other register and error counter remain unchanged. note: set the bit timing register (btr) after halting the bus. bit 1 reserved: reserved bit always set this bit to 0. read: 0 is always read. bit 2 nie: node status transition interrupt output enable bit this bit controls generation of a node status transition interrupt when the node status transits (csr: nt = 1). when set to 0: disables interrupt generation when set to 1: enables interrupt generation bit 3 to bit 6 unused bits read: value not fixed write: no effect .com .com .com .com 4 .com u datasheet
441 chapter 15 can controller bit 7 toe: transmit output enable bit this bit switches between the general-purpose i/o port and the transmit pin (tx). when set to 0: functions as general-purpose i/o port when set to 1: functions as transmit pin (tx) table 15.3-3 functions of control status register (low) (csr: l) (2/2) bit name function .com .com .com .com 4 .com u datasheet
442 chapter 15 can controller 15.3.3 last event indicate register (leir) this register indicates the state of the last event. last event indicate register (leir) figure 15.3-6 last event indicate register (leir) note: when any of the node status transition bit (nte) , transmission complete bit (tce), and reception complete bit (rce) corresponding to the last event is set to 1, other bits are set to 0. reset value 000xx000 b 4 5321 bit 7 6 0 r/w r/w r/w ? ? r/w r/w bit 5 bit 2 bit 6 bit 7 r/w mbp1 1 0 0 0 1 mbp0 message buffer pointer bits 1 1 0 message buffer 0 message buffer 1 message buffer 2 message buffer 3 1 0 0 0 1 1 1 0 0 mbp2 0 0 0 1 1 1 1 message buffer 4 message buffer 5 message buffer 6 message buffer 7 rce 0 1 last event = reception complete bit reception is not completed. reception is completed. tce 0 1 last event = transmission complete bit transmission is not completed. transmission is completed. nte 0 1 last event = node status transition bit no node status transition node status transition bit 1 bit 0 r/w : read/write x : undefined ? : unused : reset value .com .com .com .com 4 .com u datasheet
443 chapter 15 can controller table 15.3-4 functions of last event indicate register (leir) bit name function bit 0 to bit 2 mbp2 to mbp0: message buffer pointer bits these bits indicate the number (x) of the message buffer where the last event occurs which is corresponding to each message buffer pointer bit. receiving completed: indicates number (x) of message buffer that completes receiving message transmitting completed: indicates number (x) of message buffer that completes transmitting message node status transition: the values of the mbp2 to mbp0 bits are invalid. when set to 0: cleared when set to 1: no effect read by read modify write instruction: 1 always read bit 3 bit 4 unused bits read: value not fixed write: no effect on operation bit 5 rce: last event reception complete bit this bit indicates that receiving the last event is completed. receiving of last event completed: sets bit to 1 when rcx bit in reception complete register set (rcr: rcx = 1) nothing is related to the setting of the reception complete interrupt enable register (rier). the number (x) of the message buffer that completes receiving the message is indicated as the last event in the mbp2 to mbp0 bits. when set to 0: cleared when set to 1: no effect read using read modify write instructions: 1 always read bit 6 tce: last event transmission complete bit this bit indicates that the transmitting the last event is completed. transmitting of last event completed: sets bit to 1 when tcx bit in transmis sion complete register set (tcr: tcx = 1) nothing is related to the setting of the transmission complete interrupt enable register (tier). the number (x) of the message buffer that completes receiving the message is indicated as the last event in the mbp2 to mbp0 bits. when set to 0: cleared when set to 1: no effect read using read modify write instruction: 1 always read bit 7 nte: last event node status transition bit this bit indicates that the last event refers to the node status transition. last event referring to node status transition: sets bit to 1 when ntx bit in control status register set (csr: ntx = 1) the nte bit is set to 1 at the same time that the tcx in the transmission complete register (tcr) is set. nothing is related to the setting of the nie bit in the control status register (csr). when set to 0: cleared when set to 1: no effect read by read modify write instruction: 1 always read note: when the last event indicate regist er (leir) is accessed in interrupt pr ocessing of the can controller, the event causing the interrupt does not always match the event indicated by the last event indicate register (leir). other event may occur before the last even t indicate register (leir) is accessed in interrupt processing after an interrupt request is generated. .com .com .com .com 4 .com u datasheet
444 chapter 15 can controller 15.3.4 receive/transmit error counter (rtec) the receive/transmit error count er (rtec) indicates the number of times an error occurs at transmitting and receiv ing the message. it counts up when transmit or receive errors occurs and counts down when trans mitting and receiv ing are performed normally. receive/transmit er ror counter (rtec) figure 15.3-7 receive/transmit error counter (rtec) r: read only bit 15 14 13 12 11 10 9 8 reset value tec7 tec6 tec5 tec4 tec3 tec2 tec1 tec0 00000000 b rrrrrrrr 76543210 reset value rec7 rec6 rec5 rec4 rec3 rec2 rec1 rec0 00000000 b rrrrrrrr table 15.3-5 functions of receive/transmit error counter (rtec) bit name function bit 0 to bit 7 rec7 to rec0: receive error counter bits receive error counter value = 96 or more: node status transits to warning (csr: ns1, ns0 = 01 b ) receive error counter value = 128 or more: node status transits to error passive (csr: ns1, ns0 = 10 b ) receive error counter value = 256 or more: stops counting up. the node status remains with error passive (csr: ns1, ns0="10 b "). bit 8 to bit 15 tec7 to tec0: transmit error counter bits transmit error counter value = 96 or more : node status transits to warning (csr: ns1, ns0 = 01 b ) transmit error counter value = 128 or more : node status transits to error passive (csr: ns1, ns0 = 10 b ) transmit error counter value = 256 or more : stops counting up. the node status tr ansits to bus off (csr: ns1, ns0 = 11 b ). .com .com .com .com 4 .com u datasheet
445 chapter 15 can controller node status transition due to error occurrence in the can controller, the node status transits accord ing to the error count of the receive/transmit error counter (rtec). figure 15.3-8 sh ows the node status transition. figure 15.3-8 node status transition error active hardware reset error passive tec 256 rec < 96 besides tec < 96 cancellation of bus operation halt is necessary for transition rec: receive error counter tec: transmit error counter rec < 128 besides tec < 128 rec 96 or tec 96 rec 128 or tec 128 bus off (halt = 1) warning (error active) after 0 was written to the halt bit of the control status register (csr), continuous 11-bit high levels (receive) are input 128 times to the receive input pin (rx) to transit. table 15.3-6 node status node status state of can bus error active normal state warning a bus fault occurs error passive bus off communications are disabled. the ca n controller is completely isolated from the can bus. (to return to the normal state, pe rform the steps in the above figure.) .com .com .com .com 4 .com u datasheet
446 chapter 15 can controller 15.3.5 bit timing register (btr) the bit timing register (btr) sets the presca ler and bit timing after halting the bus (csr: halt = 1). bit timing register (btr) figure 15.3-9 bit timing register (btr) r/w: read/write x: undefined -: unused bit 15 14 13 12 11 10 9 8 reset value ts2.2 ts2.1 ts2.0 ts1.3 ts1.2 ts1.1 ts1.0 x1111111 b - r/w r/w r/w r/w r/w r/w r/w 76543210 reset value rsj1 rsj0 psc5 psc4 psc3 psc2 psc1 psc0 11111111 b r/w r/w r/w r/w r/w r/w r/w r/w table 15.3-7 functions of bit timing register (btr) bit name function bit 0 to bit 5 psc5 to psc0: prescaler setting bits 5 to 0 these bits divide the frequency of the system clock to determine the time quantum (tq) of the can controller. bit 6 to bit 7 rsj1, rsj0: resynchronous jump width setting bits 1, 0 these bits set the resynchronous jump width (rsjw). bit 8 to bit 11 ts1.3 to ts1.0: time segment 1 setting bits 3 to 0 these bits set the time of time segment 1 (tseg1). time segment 1 is equivalent to propagation segment (prop_seg) and phase buffer segment 1 (phase_seg1) based on can specifications. bit 12 to bit 14 ts2.2 to ts2.0: time segment 2 setting bits 2 to 0 these bits set the time of time segment 2 (tseg2). time segment 2 is equivalent to phase buffer segment 2 (phase_seg2) based on can specifications. note: set the bit timing register (btr) after halting the bus (csr: halt = 1). after setting the bit timing register (btr), write 0 to the halt bit in the control status register to cancel the bus halt. .com .com .com .com 4 .com u datasheet
447 chapter 15 can controller definition of bit timing segment bit timing is set in the bit timing register (btr). figure 15.3-10 and figure 15.3-11 show the segments of the nominal bit time (one bit of time with in message) and bit timing register (btr). bit time segments of general can specifications figure 15.3-10 bit time segmen ts of general can specifications sync_seg (sync segment): synchronization is performed to shorten or prolong the bit time. prop_seg (propagation segment): the physical delay among networks is adjusted. phase_seg (phase segment): the phase shif t due to oscillation errors is adjusted. bit time segments of fujitsu can controller the propagation segment (prop_ seg) and phase segment 1 (phas e_seg1) are used as the time segment 1 (tseg1). the phase se gment 2 (phase_seg2) is used as the time segment 2 (tseg2). figure 15.3-11 bit time segments of can controller tseg1 = prop_seg + phase_seg1 tseg2 = phase_seg2 sync_seg (sync segment) prop_seg (propagation segment) phase_seg1 (phase segment 1) phase_seg2 (phase segment 2) sampling point nominal bit time sync_seg (sync segment) tseg1 (time segment 1) tseg2 (time segment 2) sampling point nominal bit time .com .com .com .com 4 .com u datasheet
448 chapter 15 can controller calculation of bit timing figure 15.3-12 and figure 15.3-13 show the calculation example of bit timing, respectively, assuming input clock (clk), time quantum (tq), bit time (bt), sy nchronous segment (sync_seg), time segments 1 and 2 (tseg1, tseg2), resynchronous jump widt h (rsjw), and frequency division (psc). figure 15.3-12 calculation of bit timing . tq = (psc + 1) clk . bt = sync_seg + tseg1 + tseg2 = (1 + (ts1 + 1) + (ts2 + 1) ) tq = (3 + ts1 + ts2) tq . rsjw = (rsj + 1) tq for each segment, the following conditions should be met. . when psc is 1 to 63 (2 to 64-divided clock) tseg1 2tq tseg1 rsjw tseg2 2tq tseg2 rsjw . when psc is 0 (1-divided clock) tseg1 5tq tseg2 2tq tseg2 rsjw .com .com .com .com 4 .com u datasheet
449 chapter 15 can controller figure 15.3-13 calculation example of bit timing (4) conditions of bit timing (bt) [bt 8tq] (unit: s) machine clock (clk) 4 mhz (0.25 s) 8 mhz (0.125 s) 16 mhz (0.0625 s) 2 1 0.5 4 2 1 6 3 1.5 8 4 2 10 5 2.5 12 6 3 14 7 3.5 16 8 4 18 9 4.5 20 10 5 22 11 5.5 24 12 6 26 13 6.5 28 14 7 30 15 7.5 8tq (unit: kbps) tseg1 + 1 1 667 500 400 333 286 250 222 200 182 167 154 143 133 125 118 111 2 500 400 333 286 250 222 200 182 167 154 143 133 125 118 111 105 3 400 333 286 250 222 200 182 167 154 143 133 125 118 111 105 100 4 333 286 250 222 200 182 167 154 143 133 125 118 111 105 100 95.2 5 286 250 222 200 182 167 154 143 133 125 118 111 105 100 95.2 90.9 6 250 222 200 182 167 154 143 133 125 118 111 105 100 95.2 90.9 87 7 222 200 182 167 154 143 133 125 118 111 105 100 95.2 90.9 87 83.3 8 200 182 167 154 143 133 125 118 111 105 100 95.2 90.9 87 83.3 80 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 (3) setting of resynchronous jump width (when resynchronous jump width is 4tq) (unit: tq) (unit: s) rsj+1 (frequency division of tq) rsjw = (rsj + 1) tq 1 0.5 2 1 3 1.5 4 2 (5) conditions of tseg2 (unit: tq) (unit: tq) (unit: s) rsjw = (rsj + 1) tq tseg2 rsjw tseg2 rsjw 1 1 0.5 2 2 1 3 3 1.5 4 4 2 (6) conditions of tseg1 tseg1 delay time + rsjw (assuming that delay time is 50ns) 2 + 4tq 5tq tseg1 5 (unit: tq) (2) calculation of bit time (bt) based on the above setting and conditions bt = sync_seg + tseg1 + tseg2 = (1 + (ts1 + 1) + (ts2+1)) tq = (3 + ts1 + ts2) tq (1) (2) (3) (4) (5) 16 15 14 13 12 4 5 6 7 8 tseg2 + 1 tseg 1 + 1 sync_seg sampling point 80% 75% 70% 65% 60% calculation of sampling point (1) (2) (3) (4) (5) sampling point examle: when 1tq is 1/20 bit timing at 100 kbps (1/100 kbps/20) condition: (resynchronous jump width is 4tq, delay time is 50 s) (1) calculations of time quantum (tq) [tq = (psc + 1) clk] (unit: s) machine clock (clk) 4 mhz (0.25 s) 8 mhz (0.125 s) 16 mhz (0.0625 s) 1 0.25 0.13 0.06 3 0.75 0.38 0.19 4 1 0.5 0.25 5 1.25 0.63 0.31 6 1.5 0.75 0.38 7 1.75 0.88 0.44 8 2 1 0.5 9 2.25 1.13 0.56 10 2.5 1.25 0.63 11 2.75 1.38 0.69 12 3 1.5 0.75 13 3.25 1.63 0.81 14 3.5 1.75 0.88 15 3.75 1.88 0.94 frequency division of input clock (psc+1) sync_seg + (tseg1 + 1) tseg2 + 1 tseg2 + 1 2 0.5 0.25 0.13 .com .com .com .com 4 .com u datasheet
450 chapter 15 can controller 15.3.6 message buffer valid register (bvalr) the message buffer valid register (bvalr) enables or disables th e message buffers and indicates their status. message buffer valid register (bvalr) figure 15.3-14 message buffer valid register (bvalr) bval0 0 1 disables message buffer 0 enables message buffer 0 message buffer enable bit 0 disables message buffer 1 enables message buffer 1 message buffer enable bit 1 reset value 00000000 b bit 0 r/w r/w r/w r/w r/w r/w r/w r/w bval1 0 1 bit 1 bval2 0 1 disables message buffer 2 enables message buffer 2 message buffer enable bit 2 r/w : read/write : reset value bit 2 bval3 0 1 disables message buffer 3 enables message buffer 3 message buffer enable bit 3 bit 3 bval4 0 1 disables message buffer 4 enables message buffer 4 disables message buffer 5 enables message buffer 5 message buffer enable bit 4 bit 4 bval5 0 1 message buffer enable bit 5 bit 5 bval7 0 1 disables message buffer 7 enables message buffer 7 message buffer enable bit 7 bit 7 bval6 0 1 disables message buffer 6 enables message buffer 6 message buffer enable bit 6 bit 6 4 5 3210 76 .com .com .com .com 4 .com u datasheet
451 chapter 15 can controller table 15.3-8 functions of message buffer enable register bit name function bit 0 to bit 7 bval7 to bval0: message buffer enable bits 7 to 0 these bits enable or disa ble transmitting and receiving of the message to and from the message buffer (x). when set to 0: no message can be transmitted and received to and from the message buffer (x). when set to 1: a message can be transmitted and received to and from the message buffer (x). [message buffer disabled (bvalx = 0)] during transmitting: transmitting and receiving are disabled after message transmitting is completed or a transmit error is terminated. during receiving: transmitting and receiving ar e disabled immediately. when the received message is stored in the message buffer, transmitting and receiving are disabled after the message is stored. note: the read modify write instructions are disabled until the bvalx bit is actually set to 0 after 0 is written to the bit. note: to invalidate the message buffer (by setting the bvalr: bval bit to 0) while can controller is participating in can communication (the read value of the csr: halt bit is 0 and can controller is ready to receive or transmit messa ges), follow the cautions in sect ion "15.6 precautio ns when using can controller". .com .com .com .com 4 .com u datasheet
452 chapter 15 can controller 15.3.7 ide register (ider) the ide register (ider) set s the frame format of the message buffer used during transmitting and receiving. transmitting and receiving are enab led in the standard frame format (id11 bits) and the ex tended frame format (id29 bits). ide register (ider) figure 15.3-15 ide register (ider) reset value r/w r/w r/w r/w r/w r/w r/w r/w x : undefined r/w : read/write used in standard fomat (id 11 bits) used in extended format (id 29 bits) id format select bit 0 (message buffer 0) used in standard fomat (id 11 bits) used in extended format (id 29 bits) id format select bit 1 (message buffer 1) used in standard fomat (id 11 bits) used in extended format (id 29 bits) id format select bit 2 (message buffer 2) used in standard fomat (id 11 bits) used in extended format (id 29 bits) id format select bit 3 (message buffer 3) used in standard fomat (id 11 bits) used in extended format (id 29 bits) id format select bit 4 (message buffer 4) used in standard fomat (id 11 bits) used in extended format (id 29 bits) id format select bit 5 (message buffer 5) used in standard fomat (id 11 bits) used in extended format (id 29 bits) id format select bit 6 (message buffer 6) used in standard fomat (id 11 bits) used in extended format (id 29 bits) id format select bit 7 (message buffer 7) ide0 bit 0 0 1 ide1 bit 1 0 1 ide2 bit 2 0 1 ide3 bit 3 0 1 ide4 bit 4 0 1 ide5 bit 5 0 1 ide6 bit 6 0 1 ide7 bit 7 0 1 xxxxxxxx b 4 5 3210 76 .com .com .com .com 4 .com u datasheet
453 chapter 15 can controller table 15.3-9 functions of ide register (ider) bit name function bit 0 to bit 7 ide7 to ide0: id format select bits 7 to 0 these bits set the id format of the message buffer (x). when set to 0: uses message buffer (x) in standard format (id11 bits) when set to 1: uses message buffer (x) in extended format (id29 bits) note: the ide register (ider) should be set after having the message buffer (x) disabled (bvalr: bvalx = 0). setting the ide register (ider) with the message buffer (x) being enabled may store message unnecessary received. note: to invalidate the message buffer (by setting the bvalr: bval bit to 0) while can controller is participating in can communication (the read value of the csr: halt bit is 0 and can controller is ready to receive or transmit messa ges), follow the cautions in sect ion "15.6 precautio ns when using can controller". .com .com .com .com 4 .com u datasheet
454 chapter 15 can controller 15.3.8 transmission request register (treqr) the transmission request regist er (treqr) sets a transmit request fo r each message buffer and indicates its status. transmission request register (treqr) figure 15.3-16 transmission request register (treqr) treq0 0 1 does not request transmission (transmission is not requested) requests transmission (transmission is requested) transmission request bit 0 (message buffer 0) reset value 00000000 b bit 0 r/w r/w r/w r/w r/w r/w r/w r/w treq1 0 1 does not request transmission (transmission is not requested) requests transmission (transmission is requested) transmission request bit 1 (message buffer 1) bit 1 treq2 0 1 does not request transmission (transmission is not requested) requests transmission (transmission is requested) transmission request bit 2 (message buffer 2) r/w : read/write : reset value bit 2 treq3 0 1 does not request transmission (transmission is not requested) requests transmission (transmission is requested) transmission request bit 3 (message buffer 3) bit 3 treq4 0 1 does not request transmission (transmission is not requested) requests transmission (transmission is requested) does not request transmission (transmission is not requested) requests transmission (transmission is requested) transmission request bit 4 (message buffer 4) bit 4 treq5 0 1 transmission request bit 5 (message buffer 5) bit 5 treq7 0 1 does not request transmission (transmission is not requested) requests transmission (transmission is requested) transmission request bit 7 (message buffer 7) bit 7 treq6 0 1 does not request transmission (transmission is not requested) requests transmission (transmission is requested) transmission request bit 6 (message buffer 6) bit 6 4 5 3210 7 6 .com .com .com .com 4 .com u datasheet
455 chapter 15 can controller table 15.3-10 functions of transmission request register (treqr) bit name function bit 0 to bit7 treq7 to treq0: transmission request bits 7 to 0 these bits starts transmitting for the message buffer (x). when set to 0: no effect when set to 1: starts transmitting for message buffer (x) if more than one transmit complete bit is set (treqx = 1), transmitting is started with the lower number of the message buffer (x) that accepts the transmit request. these bits remain 1s during the transm it being requested and are cleared to 0 when transmitting is completed or the transfer request is cancelled. clearing a transmit request when transmitting is completed (treqx = 0) overrides setting of the transmit request bit when 0 is written (treqx = 1) if both occur at the same time. read by read modify write instruction: 1 always read [setting of remote frame receive wait bit (rfwtr: rfwtx)] rfwtx bit = 0: starts transmitting immediately even if rrtrx bit in receive rtr register = 1 rfwtx bit = 1: starts transmitting after remote frame received. references: see "15.3.10 remote frame receiving wait register (rfwtr)" for details of the remote frame receive wait register (rfwtr). see "15.3.15 reception rtr register (rrtrr)" for details of the receive rtr register (rrtrr). see "15.3.11 transmission cancel register (tc anr)" and "15.5.1 transmission" for details about the transmit cancellation. .com .com .com .com 4 .com u datasheet
456 chapter 15 can controller 15.3.9 transmission rtr register (trtrr) this register sets the frame format of transmit message for the message buffers. transmission rtr register (trtrr) figure 15.3-17 transmission rtr register (trtrr) reset value r/w r/w r/w r/w r/w r/w r/w r/w transmits as data frame transmits as remote frame remote frame setting bit 0 (message buffer 0) transmits as data frame transmits as remote frame remote frame setting bit 1 (message buffer 1) transmits as data frame transmits as remote frame remote frame setting bit 2 (message buffer 2) transmits as data frame transmits as remote frame remote frame setting bit 3 (message buffer 3) transmits as data frame transmits as remote frame remote frame setting bit 4 (message buffer 4) transmits as data frame transmits as remote frame remote frame setting bit 5 (message buffer 5) transmits as data frame transmits as remote frame remote frame setting bit 6 (message buffer 6) transmits as data frame transmits as remote frame remote frame setting bit 7 (message buffer 7) trtr0 bit 0 0 1 trtr1 bit 1 0 1 trtr2 bit 2 0 1 trtr3 bit 3 0 1 trtr4 bit 4 0 1 trtr5 bit 5 0 1 trtr6 bit 6 0 1 trtr7 bit 7 0 1 00000000 b r/w : read/write : reset value 4 5 3210 76 .com .com .com .com 4 .com u datasheet
457 chapter 15 can controller when 0 is written to each bit in the transmit rtr re gister (trtrr), the data fr ame format is set. when 1 is written to each bit, the remote frame format is set. table 15.3-11 functions of transmission rtr register (trtrr) bit name function bit 0 to bit 7 trtr7 to trtr0: remote frame setting bits 7 to 0 these bits set the transfer format of the message buffer (x) for transmitting or receiving. when set to 0: sets data frame format when set to 1: sets remote frame format .com .com .com .com 4 .com u datasheet
458 chapter 15 can controller 15.3.10 remote frame receiving wait register (rfwtr) remote frame receiving wait r egister (rfwtr) sets whether th is register waits remote frame receiving when transmission request of data frame is set. remote frame receiving wait register (rfwtr) figure 15.3-18 remote frame receive wait register (rfwtr) reset value r/w r/w r/w r/w r/w r/w r/w r/w transmission starts immediately transmission starts after receiving remote frame remote frame receiving wait bit 0 (message buffer 0) transmission starts immediately transmission starts after receiving remote frame remote frame receiving wait bit 1 (message buffer 1) transmission starts immediately transmission starts after receiving remote frame remote frame receiving wait bit 2 (message buffer 2) transmission starts immediately transmission starts after receiving remote frame remote frame receiving wait bit 3 (message buffer 3) transmission starts immediately transmission starts after receiving remote frame remote frame receiving wait bit 4 (message buffer 4) transmission starts immediately transmission starts after receiving remote frame remote frame receiving wait bit 5 (message buffer 5) transmission starts immediately transmission starts after receiving remote frame remote frame receiving wait bit 6 (message buffer 6) transmission starts immediately transmission starts after receiving remote frame remote frame receiving wait bit 7 (message buffer 7) rfwt0 bit 0 0 1 rfwt1 bit 1 0 1 rfwt2 bit 2 0 1 rfwt3 bit 3 0 1 rfwt4 bit 4 0 1 rfwt5 bit 5 0 1 rfwt6 bit 6 0 1 rfwt7 bit 7 0 1 xxxxxxxx b r/w : read/write : reset vlaue 4 5 3210 76 .com .com .com .com 4 .com u datasheet
459 chapter 15 can controller table 15.3-12 functions of remote frame receiving wait register (rfwtr) bit name function bit 0 to bit 7 rfwt7 to rfwt0: remote frame receiving wait bits 7 to 0 these bits set whether to wait for reception of a remote frame for the message buffer (x) for which a request to transmit a data frame is set. when set to 0: starts transmitting immediately for message buffer (x) for which a request to transmit data frame is set transmitting is started immediately ev en if the receive rtr register is already set in the message buffer (x) (rrtrr: rrtrx = 1). when set to 1: starts transmitting after remote frame is received in message buffer (x) in which a request to transmit a data frame is set. note: when transmitting a remote frame, do not write 1 to the rfwtx bit. references: see "15.3.8 transmission request register (treqr)" for details of the transmission request register (treqr). see "15.3.9 transmission rtr re gister (trtrr)" for details of the transmission rtr register (trtrr). see "15.3.15 reception rtr register (rrtrr)" for details of the receive rtr register (rrtrr). .com .com .com .com 4 .com u datasheet
460 chapter 15 can controller 15.3.11 transmission cancel register (tcanr) the transmission cancel register (tcanr) sets cancellati on of a transmission request for the message buffer in the transmit wait state. transmission cancel register (tcanr) figure 15.3-19 transmission cancel register (tcanr) tcan0 0 1 no effect cancels transmission request of message buffer 0 transmission cancel bit 0 reset value 00000000 b bit 0 w w w w w w w w tcan1 0 1 no effect cancels transmission request of message buffer 1 transmission cancel bit 1 bit 1 tcan2 0 1 no effect cancels transmission request of message buffer 2 transmission cancel bit 2 w : write only : reset value bit 2 tcan3 0 1 no effect cancels transmission request of message buffer 3 transmission cancel bit 3 bit 3 tcan4 0 1 no effect cancels transmission request of message buffer 4 no effect cancels transmission request of message buffer 5 transmission cancel bit 4 bit 4 tcan5 0 1 transmission cancel bit 5 bit 5 tcan7 0 1 no effect cancels transmission request of message buffer 7 transmission cancel bit 7 bit 7 tcan6 0 1 no effect cancels transmission request of message buffer 6 transmission cancel bit 6 bit 6 4 5 3210 76 .com .com .com .com 4 .com u datasheet
461 chapter 15 can controller table 15.3-13 functions of transmission cancel register (tcanr) bit name function bit 0 to bit 7 tcan7 to tcan0: transmission cancel bits 7 to 0 these bits cancel a transmission reques t for the message buffer (x) in the transmit wait state. when set to 0: no effect when set to 1: cancels transmission requ est for message buffer (x) when a transmission request is cancelled by setting 1 to the tcanx bit, the treqx bit corresponding to the messa ge buffer (x) is cleared (treqx = 0) for which transmissi on request is cancelled. read: 0 always read note: the transmission cancel register (tcanr) is a write-only register. .com .com .com .com 4 .com u datasheet
462 chapter 15 can controller 15.3.12 transmission complete register (tcr) the transmission complete regist er (tcr) indicat es whether transmitt ing a data from the message buffer completes. when an output of interrupt requ est is enabled at completing transmitting, an inte rrupt request is output when transmitting is completed. transmission complete register (tcr) figure 15.3-20 transmission complete register (tcr) tc0 0 1 transmission is not completed/no transmission transmission is completed transmission complete bit 0 (message buffer 0) reset value 00000000 b bit 0 r/w r/w r/w r/w r/w r/w r/w r/w tc1 0 1 transmission is not completed/no transmission transmission is completed transmission complete bit 1 (message buffer 1) bit 1 tc2 0 1 transmission is not completed/no transmission transmission is completed transmission complete bit 2 (message buffer 2) r/w : read/write : reset value bit 2 tc3 0 1 transmission is not completed/no transmission transmission is completed transmission complete bit 3 (message buffer 3) bit 3 tc4 0 1 transmission is not completed/no transmission transmission is completed transmission is not completed/no transmission transmission is completed transmission complete bit 4 (message buffer 4) bit 4 tc5 0 1 transmission complete bit 5 (message buffer 5) bit 5 tc7 0 1 transmission is not completed/no transmission transmission is completed transmission complete bit 7 (message buffer 7) bit 7 tc6 0 1 transmission is not completed/no transmission transmission is completed transmission complete bit 6 (message buffer 6) bit 6 4 53210 76 .com .com .com .com 4 .com u datasheet
463 chapter 15 can controller table 15.3-14 functions of transmission complete register (tcr) bit name function bit 0 to bit 7 tc7 to tc0: transmission complete bits 7 to 0 these bits indicate whether the message buffer (x) completes transmitting message. when message transmitting completed: 1 is set to the tcx bit correspondi ng to the message buffer (x) that completes transmitting. when set to 0: clears bits if transmitting already completed when set to 1: no effect read by read modify write instruction: 1 always read setting the tcx bit when transmitting is completed (tcx = 1) overrides clearing of the tcx bit when 0 is written (tcx = 0) if both occur at the same time. when the treqx bit in the transmit request register (treqr) is set (treqr: treqx = 1), the tcx bit is cleared (tcx = 0). [generation of transmissi on complete interrupt] if the transmit complete interrupt enable register (tier) is set (tier: tiex = 1), a transmit complete interrupt is generated when transmitting is completed (tcr: tcx = 1). .com .com .com .com 4 .com u datasheet
464 chapter 15 can controller 15.3.13 transmission complete in terrupt enable register (tier) the transmission complete interrupt enable register (tier) enab les or disables a transmit complete interrupt for each message buffer. transmission complete interr upt enable register (tier) figure 15.3-21 transmission complete interrupt enable register (tier) reset value r/w r/w r/w r/w r/w r/w r/w r/w disables transmission complete interrupt enables transmission complete interrupt transmission interrupt enable bit 0 (message buffer 0) disables transmission complete interrupt enables transmission complete interrupt transmission interrupt enable bit 1 (message buffer 1) disables transmission complete interrupt enables transmission complete interrupt transmission interrupt enable bit 2 (message buffer 2) disables transmission complete interrupt enables transmission complete interrupt transmission interrupt enable bit 3 (message buffer 3) disables transmission complete interrupt enables transmission complete interrupt transmission interrupt enable bit 4 (message buffer 4) disables transmission complete interrupt enables transmission complete interrupt transmission interrupt enable bit 5 (message buffer 5) disables transmission complete interrupt enables transmission complete interrupt transmission interrupt enable bit 6 (message buffer 6) disables transmission complete interrupt enables transmission complete interrupt transmission interrupt enable bit 7 (message buffer 7) tie0 bit 0 0 1 tie1 bit 1 0 1 tie2 bit 2 0 1 tie3 bit 3 0 1 tie4 bit 4 0 1 tie5 bit 5 0 1 tie6 bit 6 0 1 tie7 bit 7 0 1 00000000 b r/w : read/write : reset value 4 5 3210 76 .com .com .com .com 4 .com u datasheet
465 chapter 15 can controller table 15.3-15 functions of transmission complete interrupt enable register (tier) bit name function bit 0 to bit 7 tie7 to tie0: transmission complete interrupt enable bits 7 to 0 these bits enable or disable a tran smission complete interrupt for the message buffer (x). when set to 0: disables transmit complete interrupt for message buffer (x) when set to 1: enables transmit complete interrupt for message buffer (x) .com .com .com .com 4 .com u datasheet
466 chapter 15 can controller 15.3.14 reception complete register (rcr) the reception complete register (rcr) indicates whether th e reception a data to the message buffer (x) completes receiving. when an interrupt is enabled at completion of receiving, an interrup t request is generated. reception complete register (rcr) figure 15.3-22 reception complete register (rcr) rc0 0 1 reception is not completed/no reception reception is completed reception complete bit 0 (message buffer 0) reset value 00000000 b bit 0 r/w r/w r/w r/w r/w r/w r/w r/w rc1 0 1 reception is not completed/no reception reception is completed reception complete bit 1 (message buffer 1) bit 1 rc2 0 1 reception is not completed/no reception reception is completed reception complete bit 2 (message buffer 2) r/w : read/write : reset value bit 2 rc3 0 1 reception is not completed/no reception reception is completed reception complete bit 3 (message buffer 3) bit 3 rc4 0 1 reception is not completed/no reception reception is completed reception is not completed/no reception reception is completed reception complete bit 4 (message buffer 4) bit 4 rc5 0 1 reception complete bit 5 (message buffer 5) bit 5 rc7 0 1 reception is not completed/no reception reception is completed reception complete bit 7 (message buffer 7) bit 7 rc6 0 1 reception is not completed/no reception reception is completed reception complete bit 6 (message buffer 6) bit 6 4 53210 76 .com .com .com .com 4 .com u datasheet
467 chapter 15 can controller table 15.3-16 functions of reception complete register (rcr) bit name function bit 0 to bit 7 rc7 to rc0: reception complete bits 7 to 0 these bits indicate whether the message buffer (x) completes message receiving. when message receiving completed: 1 is set to the rcx bit corresponding to the message buffer (x) that completes receiving. when set to 0: clears bits when receiving already completed when set to 1: no effect read by read modify write instruction: 1 always read setting the rcx bit when receiving is complete d (rcx = 1) overrides clearing of the rcx bit when 0 is wr itten (rcx = 0) if both occur at the same time. [generation of reception complete interrupt] if the reception complete enable register is set (rier: riex = 1), a reception complete interrupt is gene rated when receiving is completed. note: to clear the reception complete register (rcr), read the received message after the completion of receiving and write 0. .com .com .com .com 4 .com u datasheet
468 chapter 15 can controller 15.3.15 reception rtr register (rrtrr) the reception rtr register (rrt rr) indicates that the remote frame is stored in the message buffer. reception rtr register (rrtrr) figure 15.3-23 reception rtr register (rrtrr) reset value r/w r/w r/w r/w r/w r/w r/w r/w remote frame is not received remote frame is received remote frame receive bit 0 (message buffer 0) remote frame is not received remote frame is received remote frame receive bit 1 (message buffer 1) remote frame is not received remote frame is received remote frame receive bit 2 (message buffer 2) remote frame is not received remote frame is received remote frame receive bit 3 (message buffer 3) remote frame is not received remote frame is received remote frame receive bit 4 (message buffer 4) remote frame is not received remote frame is received remote frame receive bit 5 (message buffer 5) remote frame is not received remote frame is received remote frame receive bit 6 (message buffer 6) remote frame is not received remote frame is received remote frame receive bit 7 (message buffer 7) rrtr0 bit 0 0 1 rrtr1 bit 1 0 1 rrtr2 bit 2 0 1 rrtr3 bit 3 0 1 rrtr4 bit 4 0 1 rrtr5 bit 5 0 1 rrtr6 bit 6 0 1 rrtr7 bit 7 0 1 00000000 b r/w : read/write : reset value 4 5 3210 76 .com .com .com .com 4 .com u datasheet
469 chapter 15 can controller table 15.3-17 functions of reception rtr register (rrtrr) bit name function bit 0 to bit 7 rrtr7 to rrtr0: remote frame receive bits 7 to 0 these bits indicate that the message buffer (x) receives a remote frame. when remote frame is received: 1 is set to the rrtrx bit corresponding to the message buffer (x) that receives a remote frame. when set to 0: cleared when receiving completed when set to 1: no effect setting the rrtrx bit when a remote frame is received (rrtrx = 1) overrides clearing of the rrtrx bit when 0 is written (rrtrx = 0) if both occur at the same time. the rrtrx bit corresponding to the message buffer (x) that receives a data frame is cleared (rrtrx = 0). if message transmitting is completed (tcr: tcx = 1), the rrtrx bit corresponding to the message buffer (x) that transmits the message is cleared (rrtrx = 0). read by read modify write instruction: 1 always read .com .com .com .com 4 .com u datasheet
470 chapter 15 can controller 15.3.16 reception overrun register (rovrr) the reception overrun register (rovrr) indicates that an overrun occurs (the corresponding message buffer is in the receive complete state. ) at storing the received message in the message buffer. reception overrun register (rovrr) figure 15.3-24 reception overrun register (rovrr) reset value r/w r/w r/w r/w r/w r/w r/w r/w overrun is not occurred overrun is occurred reception overrun bit 0 (message buffer 0) overrun is not occurred overrun is occurred reception overrun bit 1 (message buffer 1) overrun is not occurred overrun is occurred reception overrun bit 2 (message buffer 2) overrun is not occurred overrun is occurred reception overrun bit 3 (message buffer 3) overrun is not occurred overrun is occurred reception overrun bit 4 (message buffer 4) overrun is not occurred overrun is occurred reception overrun bit 5 (message buffer 5) overrun is not occurred overrun is occurred reception overrun bit 6 (message buffer 6) overrun is not occurred overrun is occurred reception overrun bit 7 (message buffer 7) rovr0 bit 0 0 1 rovr1 bit 1 0 1 rovr2 bit 2 0 1 rovr3 bit 3 0 1 rovr4 bit 4 0 1 rovr5 bit 5 0 1 rovr6 bit 6 0 1 rovr7 bit 7 0 1 00000000 b r/w : read/write : reset value 4 5 3210 76 .com .com .com .com 4 .com u datasheet
471 chapter 15 can controller table 15.3-18 functions of reception overrun register (rovrr) bit name function bit 0 to bit 7 rovr7 to rovr0: reception overrun bits 7 to 0 these bits indicate that an overrun occu rs at storing the received message in the message buffer that had completed receiving. at overrun: 1 is set to the rovrx bit corresponding to the message buffer (x) where an overrun occurs. when set to 0: cleared when 0 is set to after reception overrun occurred when set to 1: no effect read by read modify write instruction: 1 always read setting the rovrx bit when an over run occurs (rovrx = 1) overrides clearing of the rovrx bit when 0 is wr itten (rovrx = 0) if both occur at the same time. .com .com .com .com 4 .com u datasheet
472 chapter 15 can controller 15.3.17 reception complete inte rrupt enable register (rier) the reception complete inte rrupt enable register (rier) enables or disables a reception complete interrupt for each message buffer. reception complete interrupt enable register (rier) figure 15.3-25 reception complete interrupt enable register (rier) reset value r/w r/w r/w r/w r/w r/w r/w r/w disables reception complete interrupt enables reception complete interrupt reception complete interrupt enable bit 0 (message buffer 0) disables reception complete interrupt enables reception complete interrupt reception complete interrupt enable bit 1 (message buffer 1) disables reception complete interrupt enables reception complete interrupt reception complete interrupt enable bit 2 (message buffer 2) disables reception complete interrupt enables reception complete interrupt reception complete interrupt enable bit 3 (message buffer 3) disables reception complete interrupt enables reception complete interrupt reception complete interrupt enable bit 4 (message buffer 4) disables reception complete interrupt enables reception complete interrupt reception complete interrupt enable bit 5 (message buffer 5) disables reception complete interrupt enables reception complete interrupt reception complete interrupt enable bit 6 (message buffer 6) disables reception complete interrupt enables reception complete interrupt reception complete interrupt enable bit 7 (message buffer 7) rie0 bit 0 0 1 rie1 bit 1 0 1 rie2 bit 2 0 1 rie3 bit 3 0 1 rie4 bit 4 0 1 rie5 bit 5 0 1 rie6 bit 6 0 1 rie7 bit 7 0 1 00000000 b r/w : read/write : reset value 4 5 3210 76 .com .com .com .com 4 .com u datasheet
473 chapter 15 can controller table 15.3-19 functions of reception complete interrupt enable register (rier) bit name function bit 0 to bit 7 rie7 to rie0: reception complete interrupt enable bits 7 to 0 these bits enable or di sable a reception complete interrupt for the message buffer (x). when set to 0: disables reception complete interrupt for message buffer (x) when set to 1: enables reception complete in terrupt for message buffer (x) .com .com .com .com 4 .com u datasheet
474 chapter 15 can controller 15.3.18 acceptance mask select register (amsr) the acceptance mask select regi ster (amsr) selects t he mask (acceptance mask) format for comparison between t he identifier (id) of the received message and the message buffer. acceptance mask select register (amsr) figure 15.3-26 acceptance mask select register (amsr) x: undefined r/w: read/write bit 15 14 13 12 11 10 9 8 reset value ams7.1 ams7.0 ams6.1 ams6.0 ams5.1 ams5.0 ams4.1 ams4.0 xxxxxxxx b r/wr/wr/wr/wr/wr/wr/wr/w 76543210 reset value ams3.1 ams3.0 ams2.1 ams2.0 ams1.1 ams1.0 ams0.1 ams0.0 xxxxxxxx b r/w r/w r/w r/w r/w r/w r/w r/w amsx.1 amsx.0 acceptance mask select bits (x = 7 to 0) 0 0 full-bit comparison 0 1 full-bit mask 1 0 uses acceptance mask register 0 (amr0) 1 1 uses acceptance mask register 1 (amr1) x (7 to 0) is message buffer's number (x). .com .com .com .com 4 .com u datasheet
475 chapter 15 can controller table 15.3-20 functions of acceptance mask select register (amsr) bit name function bit 0 to bit 15 ams7.0 to ams0.0, ams7.1 to ams0.1: acceptance mask select bits 7.0 to 0.0, 7.1 to 0.0 these bits select the mask (acceptanc e mask) format for comparison between the received message id and message buff er id (idr) for the message buffer (x). no comparison with masked bits is made. full-bit comparison: all bits are compared in collating the setting values of the id register (idr) with the received message id. full-bit masking: all bits for the setting values of the id register (idr) and the received message id are masked. using acceptance mask register 0 (or 1): the acceptance mask register 0 or 1 (amr0 or amr1) is used as an acceptance mask filter. at collating the setting values of the id register (idr) with the received message id , only the bits set to 0 and corresponding to the amx bit in the acceptance mask register are compared and the bits set to 1 a nd corresponding to the amx bit are masked. if the amsx.1 and amsx.0 bits are set to 10 b or 11 b , always set the acceptance mask register (amr0 or amr1) to be used, too. note: the acceptance mask select register (amsr) should be set after disabling the message buffer (x) to be set (bvalr: bvalx = 0). setting the acceptance mask select re gister (amsr) with the message buffer (x) enabled may store a message unnecessary received. note: to invalidate the message buffer (by setting the bvalr: bval bit to 0) while can controller is participating in can communication (the read value of the csr: halt bit is 0 and can controller is ready to receive or transmit messa ges), follow the cautions in sect ion "15.6 precautio ns when using can controller". .com .com .com .com 4 .com u datasheet
476 chapter 15 can controller 15.3.19 acceptance mask register (amr) the can controller has two accept ance mask register s (amr0 and amr1). both of them can be used in the standard fram e format (id11 bits, am28 to am18) and the extended frame format (id29 bits, am28 to am0). acceptance mask register (amr) figure 15.3-27 acceptance mask register (amr) r/w: read/write x : undefined - : unused : used bits in the standard frame format bit 76543210 reset value byte0 am28 am27 am26 am25 am24 am23 am22 am21 xxxxxxxx b r/w r/w r/w r/w r/w r/w r/w r/w bit 15 14 13 12 11 10 9 8 reset value byte1 am20 am19 am18 am17 am16 am15 am14 am13 xxxxxxxx b r/w r/w r/w r/w r/w r/w r/w r/w bit 76543210 reset value byte2 am12 am11 am10 am9 am8 am7 am6 am5 xxxxxxxx b r/w r/w r/w r/w r/w r/w r/w r/w 15 14 13 12 11 10 9 8 reset value byte3 am4 am3 am2 am1 am0 xxxxxxxx b r/w r/w r/w r/w r/w ??? .com .com .com .com 4 .com u datasheet
477 chapter 15 can controller table 15.3-21 functions of acceptance mask register (amsr) bit name function bit 0 to bit 7 am21 to am 28: acceptance mask bits 28 to 21 (byte0) these bits set whether to compare or mask each bit at collating the acceptance code set in the id register (idr: idx) with the received message id. if the amsx.1 or amsx.0 bits of accep tance mask select registers are set to 10 b or 11 b , always set the acceptance mask register (amr0 or amr1) to be used, too. standard frame format (ider: idex = 0): 11 bits from am28 to am18 are used. extended frame format (ider: idex = 1): 29 bits from am28 to am0 are used. when amx bit set to 0 (compare): the bits corresponding to the amx bit set to 0 are compar ed at collating the acceptance code set in the id regi ster (idr: idx) with the received message id. when amx bit set to 1 (mask): the bits corresponding to the amx bit set to 1 are masked at collating the acceptance code set in the id regist er (idr: idx) with the received message id. note: the acceptance mask select register (amr0, amr1) should be set after disabling the message buffer (x) to be set (bvalr: bvalx = 0). setting the acceptance mask select register (amr) with the message buffer (x) enabled may store a message unnecessary received. bit 8 to bit 15 am20 to am 13: acceptance mask bits 20 to 13 (byte1) bit 0 to bit 7 am12 to am 5: acceptance mask bits 12 to 5 (byte2) bit 11 to bit 15 am4 to am 0: acceptance mask bits 4 to 0 (byte3) note: to invalidate the message buffer (by setting the bvalr: bval bit to 0) while can controller is participating in can communication (the read value of the csr: halt bit is 0 and can controller is ready to receive or transmit messa ges), follow the cautions in sect ion "15.6 precautio ns when using can controller". .com .com .com .com 4 .com u datasheet
478 chapter 15 can controller 15.3.20 message buffers the message buffers consist of id register, dlc register, and data register are used for transmission/recepti on of the message. message buffers there are 8 message buffers. one message buffer (x) (x = 0 to 7) consists of an id register (idrx), dlc register (dlcrx), and data register (dtrx). the message buffer (x) is used to transmit and receive messages. higher priority is given to smaller number message buffer. - at transmitting, if a transmit request is generate d to more than one message buffer, transmitting is started from the message buffer with the smallest number. - at receiving, if the received message id passes the acceptance filter (which compares received message id with message buffer id after acceptance ma sking) set in more than one message buffer, a received message is stored in the mess age buffer with the smallest number. if the same acceptance filter is set in more than on e message buffer, it can be used as multiple message buffers. this provid es sufficient time to perform receiving. notes: write by words to the message buffer area and general-purpose ram area. at writing by bytes, undefined data is written to the upper bytes and writing to the upper bytes is ignored when writing to the lower bytes is performed. the message buffer (x) area disabled by the messag e buffer enable register (bvalr: bvalx = 0) can be used as a general-purpose ram area. however, during transmitting or receiving, it may take up to 64 machine cycles to access the message buffer area and general-purpose ram area. references: see "15.5.1 transmission". see "15.5.2 reception". see "15.5.4 setting multiple me ssage receiving" for details of th e configuration of the multiple message buffer. .com .com .com .com 4 .com u datasheet
479 chapter 15 can controller 15.3.21 id register (idrx, x = 7 to 0) the id register (idr ) sets the id of t he message buffer used for transmitting and receiving. in the standa rd frame format, 11 bits from id 28 to id18 are used, and in the extended frame format, 29 bits from id28 to id0 are used. id register (idr) figure 15.3-28 id register (idr) r/w: read/write x : undefined - : unused : used bits in the standard frame format bit 76543210 reset value byte0 id28 id27 id26 id25 id24 id23 id22 id21 xxxxxxxx b r/w r/w r/w r/w r/w r/w r/w r/w bit 15 14 13 12 11 10 9 8 reset value byte1 id20 id19 id18 id17 id16 id15 id14 id13 xxxxxxxx b r/w r/w r/w r/w r/w r/w r/w r/w 76543210 reset value byte2 id12 id11 id10 id9 id8 id7 id6 id5 xxxxxxxx b r/w r/w r/w r/w r/w r/w r/w r/w bit 15 14 13 12 11 10 9 8 reset value byte3 id4 id3 id2 id1 id0 xxxxxxxx b r/w r/w r/w r/w r/w ??? .com .com .com .com 4 .com u datasheet
480 chapter 15 can controller table 15.3-22 functions of id register (idr) bit name function bit 0 to bit 7 id28 to id21: id bits 28 to 21 (byte0) these bits set the acceptance code or trans mit message id to be collated with the received message id. standard frame format (ider: idex = 0): 11 bits from id28 to id18 are used. the old messages left in the receive shift register are stored in id17 to id0. this will not affect the operation. all received message ids are stored even if specific bits are masked. extended frame format (ider: idex = 1): 29 bits from id28 to id0 are used. notes: when using the standard frame format (ider: idex = 0), the bits from id28 to id22 cannot be all set to 1. when setting the id register (idr), perform writing by words. writing by bytes is disabled. the id register (idr) should be set after disabling the message buffer (x) to be set (bvalr: bvalx = 0). setting the id register (idr) with the message buffer (x) enabled may st ore a message unnecessary received. bit 8 to bit 15 id20 to id13: id bits 20 to 13 (byte1) bit 0 to bit 7 id12 to id5: id bits 28 to 21 (byte2) bit 11 to bit 15 id4 to id 0: id bits 4 to 0 (byte3) .com .com .com .com 4 .com u datasheet
481 chapter 15 can controller setting example of id register (idr) table 15.3-23 gives a setting example of the id register (idr) in the standard and extended frame formats. table 15.3-23 example of id setting in standard and extended frame formats id (dec) id (hex) byte0 00 00 00 00 00 00 00 01 01 01 03 03 04 0c 0c 19 ff ff ff ff ff byte1 20 40 60 80 a0 c0 e0 00 20 40 c0 e0 00 80 a0 00 60 80 a0 c0 e0 id (dec) id (hex) byte0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ff ff ff ff ff ff ff byte1 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 01 ff ff ff ff ff ff ff byte2 00 00 00 00 00 00 00 00 00 00 00 00 01 03 03 06 3f 3f 3f 3f 3f ff ff 00 fc fd fd fe fe ff ff byte3 08 10 18 20 28 30 38 40 48 50 f0 f8 00 20 28 40 d8 e0 e8 f0 f8 f0 f8 00 80 00 80 00 80 00 80 1 2 3 4 5 6 7 8 9 10 30 31 32 100 101 200 2043 2044 2045 2046 2047 1 2 3 4 5 6 7 8 9 a 1e 1f 20 64 65 c8 7fb 7fc 7fd 7fe 7ff 1 2 3 4 5 6 7 8 9 10 30 31 32 100 101 200 2043 2044 2045 2046 2047 8190 8191 8192 536870905 536870906 536870907 536870908 536870909 536870910 536870911 1 2 3 4 5 6 7 8 9 a 1e 1f 20 64 65 c8 7fb 7fc 7fd 7fe 7ff 1ffe 1fff 2000 1ffffff9 1ffffffa 1ffffffb 1ffffffc 1ffffffd 1ffffffe 1fffffff extended frame format standard frame format .com .com .com .com 4 .com u datasheet
482 chapter 15 can controller 15.3.22 dlc register (dlcr) the dlc register (dlcr) set s the data length of the m essage to be transmitted or received. dlc register (dlcr) figure 15.3-29 dlc register (dlcr) r/w: read/write x : undefined - : unused bit 7 bit 6 bit 5 bit 4 bit 3 b it 2 bit 1 bit 0 reset value dlc3 dlc2 dlc1 dlc0 xxxxxxxx b ----r/wr/wr/wr/w table 15.3-24 functions of dlc register (dlcr) bit name function bit 0 to bit 3 dlc3 to dlc0: data length setting bits these bits set the data length (byte count) of the message to be transmitted or received. when data frame transmitted: the data length (byte count) of the transmit message is set. when remote frame transmitted: the data length (byte count) of the request message is set. when data frame received: the data length (byte count) of the received message is stored. when remote frame received: the data length (byte count) of the request message is stored. notes: the data length should be set within the range of 0 to 8 bytes. when setting the dlc register (dlcr), write by words. writing by bytes is disabled. .com .com .com .com 4 .com u datasheet
483 chapter 15 can controller 15.3.23 data register (dtr) the data register (dtr) sets t he messages at transmitting or receiving a data frame. the data length can be se t from 0 to 8 bytes. data register (dtr) figure 15.3-30 data register (dtr) r/w: read/write x : undefined bit 76543210 reset value byte0 d7 d6 d5 d4 d3 d2 d1 d0 xxxxxxxx b r/w r/w r/w r/w r/w r/w r/w r/w to bit 15 14 13 12 11 10 9 8 reset value byte1 d7 d6 d5 d4 d3 d2 d1 d0 xxxxxxxx b r/w r/w r/w r/w r/w r/w r/w r/w table 15.3-25 functions of data register (dtr) bit name function bit 0 to bit 15 d7 to d0 (byte7 to byte0): data bits 7 to 0 the data register (dtrx) is used only for transmitting or receiving a data frame, and is not used for a remote frame. the transmit message is set up to 8 bytes. the message is transmitted on an msb-first basis star ting with the small me ssage buffer number (byte0 to byte7). the received message is stored on an msb-first basis starting with the small message buffer number (byte0 to byte7). if the received message is less than 8 bytes, undefined data is stored in the rest of the bytes of the data register (dtrx). however this does not affect the operation. note: when setting the data register (dtr ), write by words. writing by bytes is disabled. .com .com .com .com 4 .com u datasheet
484 chapter 15 can controller 15.4 interrupts of can controller the can controller has a transmit complete interrupt, re ceive complete interrupt and node state transition interrupt, and can generate interrupts when; the transmission complete bit (tcr: tcx) is set. the reception complete bi t (rcr: rcx) is set. the node status transition flag (csr: nt) is set. interrupts of can controller table 15.4-1 shows the interrupt control bits and interrupt factors of the can controller. transmission complete interrupt when message transmitting is completed, 1 is set to the tcx bit in the transmission complete register (tcr). when a transmission complete interrupt is enabled (tier: tiex = 1) and when tcx = 1, a transmission complete interrupt is generated. when a transmission request to the message buffer is set (treqr: treqx = 1), the tcx bit in the transmission complete register (tcr) is automatically cleared to 0. when 0 is written to the tcx bit in the transmission complete register (tcr) after the completion of message transmitting (tcr: tcx = 1), the tcx bit is cleared. reception complete interrupt when message receiving is co mpleted, 1 is set to the rcx bit in th e receive complete register (rcr). when a reception complete interrupt is enabled (rier: riex = 1) and when rcx = 1, a reception complete interrupt is generated. when 0 is written to the rcx bit in the reception complete register (rcr) after the completion of message receiving (rcr: rcx = 1), the rcx bit is cleared. table 15.4-1 interrupt control bits and interrupt factors of can controller transmit/ receive interrupt flag bit interrupt factor interrupt enable bit clearing of interrupt request flag transmit transmission complete bit tcr: tcx=1 message transmitting complete transmission complete interrupt enable bit tier: tiex = 1 setting transmission request bit (treqr: treqx = 1) writing 0 to transmission complete bit (tcr: tcx) receive reception complete bit rcr: rcx=1 message receiving complete reception complete interrupt enable bit rier: riex=1 writing 0 to reception complete bit (rcr: rcx) transmit node status transition flag csr: nt=1 node status transition node status transition interrupt enable bit csr: nie=1 writing 0 to node status transition flag (csr: nt) .com .com .com .com 4 .com u datasheet
485 chapter 15 can controller node status transition interrupt when the node status of the can controller changes, 1 is set to the nt bit in the control status register (csr). if a node status tr ansition interrupt is enabled (csr: nie = 1) when nt = 1, a node status transition interrupt is generated. when 0 is written to the nt b it in the control status regi ster the nt bit is cleared. registers and vector tables relat ed to interrupt of can controller see "3.5 interrupt" for details of the interrupts. .com .com .com .com 4 .com u datasheet
486 chapter 15 can controller 15.5 explanation of operation of can controller this section explains the procedures for trans mitting and receiv ing messages and the setting of bit timing, frame format, id and acceptance filter. explanation of operati on of can controller the following sections provide more details of the operation of can controller. transmission of message (see s ection "15.5.1 transmission") reception of message (see s ection "15.5.2 reception") procedures for transmission/recepti on of message (see section "15.5.3 procedures for transmitting and receiving") reception of multiple message (see section "1 5.5.4 setting multiple message receiving") .com .com .com .com 4 .com u datasheet
487 chapter 15 can controller 15.5.1 transmission figure 15.5-1 shows a transmission flowchart. transmission figure 15.5-1 transmission flowchart transmission request set? (treqr : treqx) set transmission request register (treqr : treqx = 1) trtrx = 1 no no no : 0 no: 0 yes : 1 trtrx = 0 no : 0 no : 0 yes : 1 yes : 1 yes: 1 no : 0 yes yes transmission complete register is cleared (tcr : tcx = 0) if there remains message buffer meeting transmission conditions, the lowest- numbered message buffer is selected. transmission request register is cleared (treqr : treqx = 0) reception rtr register is cleared (rrtrr : rrtrx = 0) transmission complete register is set (tcr : tcx = 1) transmission cancelled? (tcanr : tcanx) transmission register is cleared (treqr : treqx = 0) remote frame receiving wait? (rfwtr : rfwtx) remote frame received? (rrtrr : rrtrx) is bus idle state? how is frame setting? (trtrr : trtrx) is transmission successful? transmission complete interrupt enabled? (tier : tiex = 1) a data frame is transmitted a remote frame is transmitted yes : 1 transmission complete interrupt request is output transmission is completed .com .com .com .com 4 .com u datasheet
488 chapter 15 can controller starting transmitting setting of transmission request to start transmitting, set the treqx bit in the transmission request register to 1 which is corresponding to the message buffer (x) that transmits the message. when the treqx bit is set, the transmission complete register is cleared (tcr: tcx = 0). presence or absence of remote frame receive wait if the rfwtx bit in the remote frame receive wait regi ster is set, transmitting is started after a remote frame is received (rrtrr: rrtrx = 1). if the remote frame receive wait register does not wait for receiving of a remote frame (rfwtr: rfwtx = 0), transmitting is started immediately after the transmission request bit is set (treqr: treqx = 1). performing transmitting transmission request set in more than one message buffer when a transmission request is set in more than one message buffer (treqr: treqx = 1), transmitting is performed starting with the small-numbered message buffer (x = 7 to 0). transmitting to can bus transmitting message to the can bus from the transmit output pin (tx) is started when the can bus is idle. arbitration arbitration is performed when a message buffer conf licts with transmitting from other can controllers on the can bus. if arbitration fails or an error oc curs during transmitting, retransmitting is performed automatically until it su cceeds after waiting until the bus goes idle again. selection of frame format when 0 is set to the trtrx bit in the transmit rtr register, a data frame is transmitted. when 1 is set to the bit, a remote frame is transmitted. canceling transmit request cancellation by transmissi on cancel register (tcanr) during transmitting message, the transmission request set in the message buffer that is not transmitted (held) can be cancelled by setting 1 in th e transmission cancel register (tcanr). when the transmission request is completely cancelled (tcanr: tcanx = 1), the transmission request register is cleared (treqx = 1). cancellation by receiving message the message buffer can receive the message even during requesting a tran smitting. however, the transmission request is cancelled under the following conditions: request to transmit data frame: when a data frame is received, th e transmission request is cancelled. when a remote frame is received, the transmission request is not cancelled. request to transmit remote frame: the transmission request is cancelled even if ei ther a data frame or remote frame is received. .com .com .com .com 4 .com u datasheet
489 chapter 15 can controller completing transmitting success of transmitting when transmitting is terminated normally, the tcx bit in the transmission complete register is set. the transmission request register and receive rtr register (treqr: treqx = 0, rrtrr: rrtrx = 0) are cleared. generation of transmission interrupt when the tiex bit in the transmission complete interrupt enable register is set, an interrupt request is generated when transmitting is completed (tcr: tcx = 1). .com .com .com .com 4 .com u datasheet
490 chapter 15 can controller 15.5.2 reception figure 15.5-2 shows a reception flowchart. reception figure 15.5-2 reception flowchart start-of-frame (sof) of data frame or remote frame is detected data frame trtrx = 1 yes no : 0 yes determine message buffer (x) where receive messages to be stored. received message is stored in the message buffer (x). transmission request register is cleared (treqr : treqx = 0) setting of reception complete register (rcr : rcx = 1) is any message buffer (x) passing through the acceptance filter found? reception complete interrupt enabled? (rier : riex = 1) transmission request of remote frame? (trtrr : trtrx) no : 0 reception complete register set? (rcr : rcx) reception overrun generation (rovrr : rovrx = 1) is reception successful? receiving message? yes : 1 no no trtrx = 0 yes : 1 remote frame clear reception rtr register (rrtrr : rrtrx = 0) set reception rtr register (rrtrr : rrtrx = 1) reception complete interrupt request is output transmission is completed .com .com .com .com 4 .com u datasheet
491 chapter 15 can controller starting receiving receiving is started when the start-of -frame (sof) of a data frame or re mote frame is detected on the can bus. acceptance filter the received message in the standard frame format is compared with the mess age buffer (x) set in the standard frame format (ider: idex = 0). the received message in the extended frame format is compared with the message buffer (x) set in the extended frame format (ider: idex = 1). passing through acceptance filter if all bits set to "compare" in the acceptance mask are matched after comparison between the received message id and acceptance code (idr: idx), the recei ved message passes the acceptance filter in the message buffer (x). storing received message if receiving message is successful, the received message is stored in the message buffer (x) that has the id that had passed the acceptance filter. data frame received the received message is stored in the id register (idr) and dlc register (dlcr), data register (dtr). if the received message is less than 8 bytes, undefined da ta is stored in the rest of the bytes in the data register (dtr). remote frame received the received message is stored in the id register (idr) and dlc register (dlcr). the data register (dtr) remains unchanged. more than one message buffer if there is more than one message buffer with the id that had passed the acceptance filter, the message buffer (x) where the received me ssage is stored is determined under the following conditions: higher priority is given to the message buffer with a smaller number (x = 0 to 7). the priority of message buffer 0 is the highest and 7 is the lowest. the received message is stored in preference to the message buffer that has not been completed receiving (rcr: rcx = 0). if the bit in the acceptance mask select register is set to "full-b it comparison" (amsx.1 = 0, 0 = 00 b ), the received message is stored in the corresponding message buffer (x), regardless of the setting value of the reception complete register (rcr: rcx). if there is more than one message buffer that has no t been completed r eceiving, or if there is more than one message buffer with the amsx.1 and amsx.0 bits in the acceptance mask select register set to 00 b (full-bit comparison), the received me ssage is stored in the message bu ffer with the smallest number (x). if there is no message buffer that satisfies the ab ove conditions, the received me ssage is stored in the message buffer with the lowest number (x). the message buffers should be arranged in order of ascending number (x) as follows; - smallest number (x): acceptance mask set to "full-bit comparison" - middle number (x): acceptan ce mask registers 0 and 1 used - largest number (x): acceptance mask set to "full-bit masking" .com .com .com .com 4 .com u datasheet
492 chapter 15 can controller setting of acceptance mask select register figure 15.5-3 flowchart of determining message buffer that stores received message table 15.5-1 setting of acceptance mask select register amsx. 1 amsx. 0 acceptance mask (x = 7 to 0) 0 0 full-bit comparison is performed. 0 1 full-bit masking is performed. 1 0 acceptance mask register 0 (amr0) is used. 1 1 acceptance mask register 1 (amr1) is used. yes no select the smallest-numbered message buffer (x) from message buffers corresponding to the above. message is not received (rcr : rcx = 0), or any message buffer set to "full-bit comparison" (amsr : amsx.1 = 0, amsx.0 = 0)? select the smallest-numbered message buffer (x). start end .com .com .com .com 4 .com u datasheet
493 chapter 15 can controller receive overrun when another received message is st ored in the message buffer that ha s completed receiving (rcr: rcx = 1), a receive overrun occu rs. when a receive overrun occurs, 1 is set to the rovrx bit in the receive overrun register corresponding to the number of the message buffer (x ) where the receive overrun occurs. processing for reception of data frame and remote frame processing for reception of data frame the reception rtr register is cleared (rrtrr: rrtrx = 0). the transmission request register is cleared (t reqr: treqx = 0) immediately before the received message is stored. a transm ission request to the message buffer (x) that does not perform transmitting is cancelled. processing for reception of remote frame the reception rtr register is set (rrtrr: rrtrx = 1). if the transmission rtr register is set (trtrr: tr trx = 1), the transmission request register is cleared (treqx = 0). the request to transmit a remote frame to the message buffer (x) that does not perform transmitting is cancelled. completing receiving when the received message is stored , the reception complete register is set (rcr: rcx = 1). if the reception complete interrupt enable register is set (rier: riex = 1), an interrupt is generated when receiving is completed (rcr: rcx = 1). note: either the request to transmit a data frame or a remote frame is cancelled. note: the request to transmit a data frame is not cancelled. for details about how to cancel a transmit request, see "canceling transmit request" in section "15.5.1 transmission". note: the can controller cannot receive any message transmitted by itself. .com .com .com .com 4 .com u datasheet
494 chapter 15 can controller 15.5.3 procedures for transmitting and receiving the section explains the procedure for transmission/receptio n of message. presetting setting of bit timing set the bit timing register (btr) after halting the bus operation (csr: halt = 1). setting of frame format set the frame format used in th e message buffer (x). when using th e standard frame format, set the idex bit in the ide register (ider) to 0. when us ing the extended frame form at, set the idex bit to 1. setting of id set the id of the message buffer (x) to the id28 to id0 bits in the id register (idr). in the standard frame format, it does not have to set the id17 to id 0 bits. the id of the mess age buffer (x) is used as the transmit message id at transmitting and as the acceptance code at receiving. set the id after disabling the message buffer (x) (bvalr: bvalx = 0). setting the id with the message buffer (x) enabled may st ore a message unnecessary received. setting of acceptance filter the acceptance filter used in the message buffer (x) is set by a combination of the acceptance code and acceptance mask. set the acceptance filter after disabl ing the message buffer (x) (bvalr: bvalx = 0). setting the acceptance filter with the message bu ffer (x) enabled may store a message unnecessary received. the acceptance mask used for each message buffer (x) is selected by the acceptance mask select register (amsr). when using the acceptance mask regi sters (amr0 and amr1), set the acceptance mask register (amr0.1), too. set the acceptance mask so that a transmissi on request will not be cancelled by storing a message unnecessary received. .com .com .com .com 4 .com u datasheet
495 chapter 15 can controller procedure for transmitti ng message buffer (x) figure 15.5-4 shows a procedur e for the transmit setting. figure 15.5-4 flowchart of procedure for transmit setting start cancel bus halt halt = 1 select message buffer to be used message buffer enable register (bvalr) set transmission complete interrupt transmission complete interrupt enable register (tier) set bit timing set frame format set id set acceptance filter bit timing register (btr) ide register (ider) id register (idr) acceptance mask select register (amsr) acceptance mask register (amr0, 1) cancellation of transmission request transmission cancel register (tcanr) transmission is completed transmission cancel end treqx tcx n n : 0 y : 1 y 0 1 0 1 is transmission successful? tcx set frame type transmission rtr register (trtrx = 0) remote frame receiving wait rfwtx = 0 store transmission data in data register data register (dtr) set frame type reception rtr register (trtrx = 1) set of transmission data length dlc register (dlcr) set request data length dlc register (dlcr) set transmission request of data frame data frame transmission (treqr) select frame type remote frame receiving wait remote frame receiving wait rfwtx = 1 transmission cancel? data frame remote frame yes no message transmission remote frame receiving wait communication error .com .com .com .com 4 .com u datasheet
496 chapter 15 can controller procedure for transmission message buffer (x) after completion of presetting, set the message buffer (x) enabled (bvalr: bvalx =1) by message buffer enable register. setting transmit data length code set the transmit data length code (byte count) to the dlc3 to dlc0 bits in the dlc register (dlcr). when transmitting a data frame (trtrr: trtrx = 0), set the data length of the transmit message. when transmitting a remote frame (trtrr: trtrx = 1), set the data length (byte count) of the message to be requested. setting transmit data (only for transmission of data frame) when transmitting a data frame (trtrr: trtrx = 0), set the data of byte count to be transmitted in the data register (dtr). setting transmission rtr register (trtrr) when transmitting a data frame, set the trtrx bit in the transmission rtr register to 0. when transmitting a remote frame, set the trtrx bit in the transmission rtr register to 1. setting conditions for starting transmitting (only in transmitting data frame) when setting the request to transmit a data frame (treqr: treqx = 1 and trtrr: trtrx = 0) and starting transmitting immediately, set the rfwtx bit in the remote frame wait register to 0. when setting the request to transmit a data frame (treqr: treqx = 1 and trtrr: trtrx = 0) and starting transmitting afte r waiting until a remote frame is received (rrtrr: rrtrx = 1), set the rfwtx bit in the remote frame wait register to 1. setting transmission complete interrupt when enabling an interrupt when transmitting is completed (tcr: tcx = 1), set the tiex bit in the transmit complete enable register to 1. when disabling an interrupt when transmitting is completed (tcr: tcx = 1), set the tiex bit in the transmission complete enable register to 0. note: setting other than "0000 b " to "1000 b " (0 to 8 bytes) is prohibited. note: rewrite transmit data after setting the treqx bit in the transmit request register to 0. there is no need to set the bit disabled in the message buffer enable re gister (bvalr: bvalx = 0). when the bit is set to disabled, no remote frame can be received. note: when the rfwt bit in the remote frame wait register is set to 1, no remote frame can be transmitted. .com .com .com .com 4 .com u datasheet
497 chapter 15 can controller canceling bus halt after the completion of setting bit timing and transmitting, write 0 to the halt bit in the control status register (csr: halt) to cancel the bus halt. setting transmission request to set a transmission request, set the treqx bit in the transmission request register to 1. canceling transmission request to cancel the transmission request held in the messa ge buffer (x), write 1 to the tcanx bit in the transmission cancel register. check the treqx bit in the tran smission request register (treqr). when the treqx bit is 0, transmission cancel is terminated or transmitting is completed. after that, check the tcx bit in the transmission complete register (tcr). if the tcx bit is 0, transmission cancel is terminated and if the tcx bit is 1, transmitting is completed. processing when transmitting completed when transmitting is successful, 1 is set to the tcx bit in the tr ansmit complete register (tcr). when a transmission complete interrupt is enabled (tier: tiex = 1), an interrupt is generated. after checking the completion of transmitting, write 0 to the tcx bit in the transmission complete register (tcr) to clear the transmission complete register (tcr). when the transmission complete register (tcr) is cleared, the transmi ssion complete interrupt is cancelled. when the message is received or stored, the he ld transmission requests are cancelled as follows: - when a data frame is received, the request to transmit a data frame is cancelled. - when a data frame is received, the request to transmit a remote frame is cancelled. - when a remote frame is received, the reque st to transmit a remote frame is cancelled. when a remote frame is received or stored, the request to transmit a da ta frame is not cancelled but the data in the id register and dlc register are rewritten to the data of the r eceived remote frame. therefore, the data in the id register and dlc register for the data frame to be transmitted are replaced by data in the received remote frame. .com .com .com .com 4 .com u datasheet
498 chapter 15 can controller procedure for receiving message buffer (x) figure 15.5-5 shows the pro cedure for the receiving setting. figure 15.5-5 flowchart of procedure for receive setting procedure for receiving message buffer (x) after presetting, perform the following setting: setting reception complete interrupt to generate a reception complete in terrupt, set the riex bit in the reception complete interrupt enable register (rier) to 1. to disable a reception comple te interrupt (rcr: rcx = 1), set th e riex bit to 0. start cancel bus halt halt = 1 select message buffer to be used message buffer enable register (bvalr) set reception complete interrupt reception complete interrupt enable register (rier) set bit timing set frame format set id set acceptance filter bit timing register (btr) ide register (ider) id register (idr) acceptance mask select register (amsr) acceptance mask register (amr0, 1) reception overrun bit clear rovrx = 0 reception complete bit clear rcx=0 end n y reception overrun? rovrx = 0? received message reading received byte count reading n y message received? rcx = 1 ? message storing (storing by reception complete interrupt) .com .com .com .com 4 .com u datasheet
499 chapter 15 can controller starting receiving to start receiving after the completio n of setting, set the bvalx bit in the message buffer enable register (bvalr) to 1 and enable the message buffer (x). canceling bus halt after the completion of setting bit timing and transmitting, write 0 to the halt bit in the control status register (csr: halt) to cancel the bus halt. processing when receiving completed if reception is successful after pa ssing through the acceptance filter, the received message is stored in the message buffer (x), 1 is set to the rcx of th e reception complete regist er (rcr). for data frame reception, rrtrx bit of the remote request receive register (rrtrr) is cleared to 0. for remote frame reception, 1 is set to the rrtrx bit. if a reception interrupt is enabled (riex of the recep tion interrupt enable re gister (rier) is 1), an interrupt is generated. process the received message after checking th e completion of receivi ng (rcr: rcx = 1). check the rovrx bit in the receive overrun regist er (rovrr) after the comp letion of processing the received message. - if the rovrx bit is set to 0, the received message is enabled. when 0 is written to the rcx bit (a reception complete interrupt is also cancelled), receiving is terminated. - if the rovrx bit is set to 1, a receive overr un occurs and the new message may overwrite the received message. when a receive overrun occurs, write 0 to the rovrx bit and then process the received message again. .com .com .com .com 4 .com u datasheet
500 chapter 15 can controller figure 15.5-6 shows an example of reception interrupt processing. figure 15.5-6 example of reception interrupt processing a = 0? received message reading interrupt generation with rcx = 1 completion a : = rovrx rovrx : = 0 rcx : 0 no yes .com .com .com .com 4 .com u datasheet
501 chapter 15 can controller 15.5.4 setting multiple message receiving when there is insufficient time to receive messages such as frequentl y received messages or messages with di fferent ids, more than on e message buffer can be combined to a multiple message buffer to give the cpu suffici ent time to process received messages. to configure multiple message buffers, per form the same setting of acceptance filter of the message buffers to be combined. setting configuration of multiple message buffer when four messages in the standard frame format are received with doing the acceptance filter of message buffers 5, 6 and 7 on the same settings, the multipl e message buffer operates as shown in the figure. note: when the acceptance mask select register is set to "full-bit comparison" (amsr: amsx.1, amsx.0 = 00 b ), do not set the same acceptance code. when the regi ster is set to "full-bit comparison", the messages are always stored in the message buffer with the sm aller number, so the message buffers cannot be formed into a multiple message buffer. .com .com .com .com 4 .com u datasheet
502 chapter 15 can controller figure 15.5-7 example of operation of multiple message buffer ide7 ider ide6 ide5 0 0 0 am28 to am18 amr0 0000 1111 111 id28 to id18 ide 0101 0000 000 0 . . . . . . . . . . . . 0 0 0101 0000 000 0101 0000 000 acceptance mask register selection initial setting message buffer 5 message buffer 6 message buffer 7 message buffer 5 message buffer 6 message buffer 7 message buffer 5 message buffer 6 message buffer 7 message buffer 5 message buffer 6 message buffer 7 message buffer 5 message buffer 6 message buffer 7 message receiving stored in message buffer 5 id28 to id18 ide 0101 1111 000 0 received message rc7 rovr7 6 5 rcr rovrr rc6 rc5 0 00 00 0 ams7 amsr ams6 ams5 10 10 10 0 0 0 0101 0000 000 0101 1111 000 0101 0000 000 rcr rovrr 0 0 00 0 message receiving stored in message buffer 6 id28 to id18 ide 0101 1111 001 0 received message 0 0 0 0101 1111 000 0101 1111 001 0101 0000 000 rcr rovrr 0 000 1 message receiving stored in message buffer 7 id28 to id18 ide 0101 1111 010 0 received message 0 0 0 0101 1111 000 0101 1111 001 0101 1111 010 rcr rovrr 0 1 1 1 0 1 0 1 message receiving reception overrun (rovr5 =1) generated, stored in message buffer 5 id28 to id18 ide 0101 1111 011 0 received message 0 0 0 0101 1111 001 0101 1111 011 0101 1111 010 rcr rovrr 0 1 0 11 1 mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .com .com .com .com 4 .com u datasheet
503 chapter 15 can controller 15.6 precautions when using can controller use of the can controller requires the following cautions. caution for disabling message buffers by bval bits the use of bval bits may affect malfunction of ca n controller when messages buffers are set disabled while can controller is participating in can communication (read value of halt bit is 0 and can controller is ready to receive or transmit messag es). this section shows the work around of this malfunction. condition when following two conditions occu r at the same time, can controll er will not perform to receive or transmit messages normally. can controller is participating in the can communi cation. (i.e. the read value of halt bit is 0 and can controller is ready to receive or transmit messages) message buffers are read or written when the message buffer s are disabled by bval bits. work around operation for re-configurin g receiving message buffers while can controller is participating in can communication (the read value of halt bit is 0 and can controller is ready to receive or transmit messages), it is nece ssary to following one from the two operations described below to re-configure message buffers by id, ams and amr0/1 register-settings. use of halt bit - write 1 to halt bit and read it back for checking the result is 1. then change the settings for id/ ams/amr0/1 registers. no use of message buffer 0 - don't use the message buffer 0. in other words, disable message buffer (bval0=0), prohibit receive interrupt (rie0=0) and do not request transmission (treq0=0). operation for processing received message don't use the receiving prohibition by bval bit to avoid over-written of next message. use the rovr bit for checking if over-write has been performed. for details, refer to section "15.3.16 reception overrun register (rovrr)" an d "15.5.3 pr ocedures for transmitting and receiving". operation for suppressing transmission request don't use bval bit for suppressing transmission request, use tcan bit instead of it. operation for composin g transmission message for composing a transmission message, it is necessary to disable the message buffer by bval bit to change contents of id and ide registers. in this case, bval bit should reset (bval=0) after checking if treq bit is 0 or after completion of the previous message transmission (tc=1). .com .com .com .com 4 .com u datasheet
504 chapter 15 can controller 15.7 program example of can controller this section shows the program example of can controller. program example of can transmission and reception processing specifications set message buffer 5 of can to data frame transm it mode and message buffe r 0 to data frame receive mode. setting of frame format : standard frame format setting of id: message buffer 0 id = 1, message buffer 5 id = 5 baud rate: 100 kbps (machine clock = 16 mhz) acceptance mask selection: full-bit comparison after entering the bus mode (halt = 0), data a0a0 h is transmitted. a transmission request is made within the transmission complete interrupt routine (treqx=1) to transmit the same data (when treqx is set to start sending, the transmission complete interrupt bit is cleared). the reception complete interrupt bit is clear ed within the recepti on interrupt routine. .com .com .com .com 4 .com u datasheet
505 chapter 15 can controller coding example : : : ;//setting of data format (can initialization) movw btr,#05cc7h ; setting baud rate 100 kbps movw ider, #0000h ; (machine clock = 1 6 mhz) ; setting of frame format ; (0: standard, 1:expanded) movw idr51,#0a000h ; setting of data frame 5 id (id = 5) movw idr01,#2000h ; setting of data frame 0 id (id = 1) movw amsr,#0000h ; acceptance mask select register ; (full-bit comparison) movw bvalr,#021h ; message buffers 5 and 0 enabled ;//transmit setting movw dlcr5,#02h ; setting of transmission data length ; (00h: 0-byte length, 0 8 h: 8 -byte length) movw rfwtr,#0000h ; remote frame receive wait register movw trtrr,#0000h ; transmission rtr register (0: data frame ; transmission, 1: remote frame transmission) movw tier,#0020h ; transmission complete interrupt enable register ;//reception setting movw rier,#0001h ; reception complete interrupt enable register ;//bus operation start mov csr0,# 8 0h ; control status register (halt=0) sthlt bbs csr0:0,sthlt ; wait until halt=0 ;//transmission data set movw dtr5,#0a0a0h ; write a0a0 h to data register of message buffer 5. movw treqr,#0020h ; transmission request register ; (1: transmission start, 0: transmission stop) : : : ;//reception complete interrupt canrx movw rcr,#0000h ; reception complete register reti ;//transmission complete interrupt cantx movw treqr,#0020h ; transmission request register ; (1: transmission start, 0: transmission stop) reti .com .com .com .com 4 .com u datasheet
506 chapter 15 can controller .com .com .com .com 4 .com u datasheet
507 chapter 16 8/16 address match detection function this chapter explains the address match detection function and its operation. 16.1 overview of addres s match detection function 16.2 block diagram of address match detection function 16.3 configuration of address match detection function 16.4 explanation of operation of address match detection function 16.5 program example of address match detection function .com .com .com .com 4 .com u datasheet
508 chapter 16 8/16 address match detection function 16.1 overview of address match detection function if the address of the instr uction to be processed next to the instruction currently processed by the program ma tches the address set in the detect address setting registers, the address match detection function forcibly r eplaces the next instruction to be processed by the program with the int9 instruction to branch to the interrupt processing program. since the address match detection function can use the int9 interrupt for instruction processing, the prog ram can be corrected by patch processing. overview of address ma tch detection function the address of the instruction to be processed next to the instruction curren tly processed by the program is always held in the address latch through the internal bus. the address match detection function always compares the value of the address he ld in the address latch with that of the address set in the detect address setting registers. when thes e compared values match, the next instruction to be processed by the cpu is forcibly replaced by the in t9 instruction, and the interrupt processing program is executed. there are two detect address setting registers (p adr0 and padr1), each of which has an interrupt enable bit. the generation of an interrupt due to a match between the address held in the address latch and the address set in the detect address setting registers can be enab led and disabled for each register. .com .com .com .com 4 .com u datasheet
509 chapter 16 8/16 address match detection function 16.2 block diagram of address match detection function the address match detectio n module consists of t he following blocks: address latch address detection control register (pacsr) detect address setting registers block diagram of address match detection function figure 16.2-1 shows the block diagram of the address match detection function. figure 16.2-1 block diagram of the address match detection function address latch the address latch stores the value of the address output to the internal data bus. address detection control register (pacsr) the address detection control regist er enables or disables output of an interrupt at an address match. detect address setting registers (padr0, padr1) the detect address setting registers set the address that is compared wi th the value of the address latch. padr0 (24bit) reserved reserved reserved ad1e reserved ad0e pacsr detect address setting register 0 address detection control register (pacsr) detect address setting register 1 address latch padr1 (24bit) int9 instruction (int9 interrupt generation) reserved reserved internal data bus reserved: always set to "0" comparator .com .com .com .com 4 .com u datasheet
510 chapter 16 8/16 address match detection function 16.3 configuration of address match detection function this section details the r egisters used by the addre ss match detection function. list of registers and r eset values of address match detection function figure 16.3-1 list of registers and reset values of address match detection function x: undefined bit76543210 address detection control register (pacsr) 00000000 bit76543210 detect address setting register 0 (padr0) : high xxxxxxxx bit151413121110 9 8 detect address setting register 0 (padr0) : middle xxxxxxxx bit76543210 detect address setting register 0 (padr0) : low xxxxxxxx bit76543210 detect address setting register 1 (padr1) : high xxxxxxxx bit151413121110 9 8 detect address setting register 1 (padr1) : middle xxxxxxxx bit76543210 detect address setting register 1 (padr1) : low xxxxxxxx .com .com .com .com 4 .com u datasheet
511 chapter 16 8/16 address match detection function 16.3.1 address detection control register (pacsr) the address detection control register (pacsr ) enables or disa bles output of an interrupt at an address ma tch. when an address match is detected when output of an interrupt at an address match is enab led, the int9 interr upt is generated. address detection cont rol register (pacsr) figure 16.3-2 address detection control register (pacsr) reset value 00000000 b 4 53210 7 6 r/w r/w r/w r/w r/w r/w r/w r/w ad0e 0 1 address match detection enable bit 0 disables address match detection in padr0 enables address match detection in padr0 bit 1 ad1e 0 1 address match detection enable bit 1 disables address match detection in padr1 enables address match detection in padr1 bit 3 reserved 0 reserved bit always set to "0" bit 4 reserved 0 reserved bit always set to "0" bit 0 reserved 0 reserved bit always set to "0" bit 2 reserved 0 reserved bit always set to "0" bit 5 reserved 0 reserved bit always set to "0" bit 6 reserved 0 reserved bit always set to "0" bit 7 r/w : read/write : reset value .com .com .com .com 4 .com u datasheet
512 chapter 16 8/16 address match detection function table 16.3-1 functions of address detection control register (pacsr) bit name function bit 0 reserved: reserved bit always set to 0. bit 1 ad0e: address match detection enable bit 0 the address match detection operatio n with the detect address setting register 0 (padr0) is enabled or disabled. when set to 0: disables the address match detection operation. when set to 1: enables the address match detection operation. when the value of detect address setting register 0 (padr0) matches with the value of address latch at enabling the address match detect operation (ad0e = 1), the int9 in struction is immediately executed. bit 2 reserved: reserved bit always set to 0. bit 3 ad1e: address match detection enable bit 1 the address match detection operatio n with the detect address setting register 1 (padr1) is enabled or disabled. when set to 0: disables the address match detection operation. when set to 1: enables the address match detection operation. when the value of detect address setting registers 1 (padr1) matches with the value of address latch at enabling the addre ss match detection operation (ad1e = 1), the int9 in struction is immediately executed. bit 4 to bit 7 reserved: reserved bit always set to 0. .com .com .com .com 4 .com u datasheet
513 chapter 16 8/16 address match detection function 16.3.2 detect address setting registers (padr0 and padr1) the value of an address to be det ected is set in the detect ad dress setting registers. when the address of the inst ruction processed by the progr am matches the address set in the detect address setting regi sters, the next i nstruction is forcibly replaced by the int9 instruction, and the interrupt processing program is executed. detect address setting r egisters (padr0 and padr1) figure 16.3-3 detect address setting registers (padr0 and padr1) r/w: read/write x: undefined bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset value padr0, padr1: high d23 d22 d21 d20 d19 d18 d17 d16 00000000 b r/w r/w r/w r/w r/w r/w r/w r/w bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 reset value padr0, padr1: middle d15 d14 d13 d12 d11 d10 d9 d8 00000000 b r r r/w r/w r/w r/w r/w r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset value padr0, padr1: low d7 d6 d5 d4 d3 d2 d1 d0 00000000 b r/w r/w r/w r/w r/w r/w r/w r/w .com .com .com .com 4 .com u datasheet
514 chapter 16 8/16 address match detection function functions of detect address setting registers there are two detect address setting registers (padr 0 and padr1) that consist of a high byte (bank), middle byte, and low byte, totaling 24 bits. in the detect address setting registers (padr0 and p adr1), starting address (first byte) of instruction to be replaced by int9 instruction should be set. figure 16.3-4 setting of starting address of instruction code to be replaced by int9 table 16.3-2 address setting of detect address setting registers register name interrupt output enable address setting detect address setting register 0 (padr0) pacsr: ad0e high set the upper 8 bits of detect address 0 (bank). middle set the middle 8 bits of detect address 0. low set the lower 8 bits of detect address 0. detect address setting register 1 (padr1) pacsr: ad1e high set the upper 8 bits of detect address 1 (bank). middle set the middle 8 bits of detect address 1. low set the lower 8 bits of detect address 1. notes: when an address of other than the first byte is set to the detect address setting register (padr0 and padr1), the instruction code is not replaced by int9 instruction and a program of an interrupt processing is not be performed. when the address is set to the second byte or subsequent, the address set by the instruction code is replaced by "01" (int9 instruction code) and, which may cause malfunction. the detect address setting registers (padr0 and padr1) should be set after disabling the address match detection (pacsr: ad0e = 0 or ad1e = 0) of corresponding address match control registers. if the detect address setting regist ers are changed without disabling the address match detection, the address match detection function will work immedi ately after an address ma tch occurs during writing address, which may cause malfunction. the address match detection function can be used only for addresses of th e internal rom area. if addresses of the external memory area are set, th e address match detection function will not work and the int9 instruction will not be executed. address ff001c : ff001f : ff0022 : instruction code mnemonic set to detect address (high : ff h , middle : 00 h , low : 1f h ) movw movw movw rw0, #0000 a, #0000 a,#0880 a8 00 00 4a 00 00 4a 80 08 .com .com .com .com 4 .com u datasheet
515 chapter 16 8/16 address match detection function 16.4 explanation of operation of address match detection function if the addresses of the instructions executed in the program match t hose set in the detection address setting regist ers (padr0 and padr1), the address match detection function will replace the fir st instruction code with the int9 instruction (01 h ) to branch to the interrupt processing program. operation of address match detection function figure 16.4-1 shows the operation of the address match detection function when the detect addresses are set and an address match is detected. figure 16.4-1 operation of address match detection function setting detect address 1. disable the detection address setting register 0 (p adr0) where the detect address is set for address match detection (pacsr: ad0e = 0). 2. set the detect address in the detection ad dress setting register 0 (padr0). set "ff h " at the higher bits of the detection address setting register 0 (padr0), "00 h " at the middle bits, and "1f h " at the lower bits. 3. enable the detect address setting register 0 (padr0) where the detect address is set for address match detection (pacsr: ad0e = 1). program execution 1. if the address of the instruction to be executed in the program matche s the set detect address, the first instruction code at the matched address is replaced by the int9 instruction code (01 h ). 2. int9 instruction is executed. int9 interrupt is generated and then interrupt processing program is executed. address ff001c : ff001f : ff0022 : replaced by int9 instruction (01 h ) instruction code a8 00 00 4a 00 00 4a 80 08 mnemonic movw movw movw rw0, #0000 a, #0000 a, #0880 the instruction address to be executed by program matches detect address setting register 0 program execution .com .com .com .com 4 .com u datasheet
516 chapter 16 8/16 address match detection function 16.4.1 example of using address match detection function this section gives an exam ple of patch processing for pr ogram correctio n using the address match det ection function. system configuration and e 2 prom memory map system configuration figure 16.4-2 gives an example of the system conf iguration using the address match detection function. figure 16.4-2 example of system configur ation using address match detection function e 2 prom mcu f 2 mc16lx storing patch program pull up resistor storing patch program from the outside connector (uart) sin serial e 2 prom interface .com .com .com .com 4 .com u datasheet
517 chapter 16 8/16 address match detection function e 2 prom memory map figure 16.4-3 shows the allocation of the patch pr ogram and data at storing the patch program in e 2 prom. figure 16.4-3 allocation of e 2 prom patch program and data patch program byte count the total byte count of the patch program (mai n body) is stored. if the byte count is "00 h ", it indicates that no patch program is provided. detect address (24 bits) the address where the instruction co de is replaced by the int9 instruct ion code due to program error is stored. this address is set in the detection address setting registers (padr0 and padr1). patch program (main body) the program executed by the int9 interrupt proces sing when the program address matches the detect address is stored. patch program 0 is allocated from any predeter mined address. patch program 1 is allocated from the address indicating
518 chapter 16 8/16 address match detection function setting and operating state initialization e 2 prom data are all cleared to "00 h ". occurrence of program error by using the connector (uart), information about the patch program is transmitted to the mcu (f 2 mc-16lx) from the outside accord ing to the allocation of the e 2 prom patch program and data. the mcu (f 2 mc-16lx) stores the information received from outside in the e 2 prom. reset sequence after reset, the mcu (f 2 mc-16lx) reads the by te count of the e 2 prom patch program to check the presence or absence of the correction program. if the byte count of the patch program is not "00 h ", the higher, middle and lowe r bits at detect addresses 0 and 1 are read and set in the detection address setting registers 0 and 1 (padr0 and padr1). the patch program (main body) is read according to the byte count of the patch program and written to ram in the mcu (f 2 mc-16lx). the patch program (main body) is allocated to the address where the patch program is executed in the int9 interrupt processing by the address match detection function. address match detection is enabled (pacsr: ad0e = 1, ad1e = 1) int9 interrupt processing interrupt processing is performed by the int9 inst ruction. the mb90385 series has no interrupt request flag by address match detection. therefore, if the st ack information in the program counter is discarded, the detect address cannot be check ed. when checking the detect addr ess, check the value of program counter stacked in the in terrupt processing routine. the patch program is executed, branching to the normal program. .com .com .com .com 4 .com u datasheet
519 chapter 16 8/16 address match detection function operation of address match detection fu nction at storing patch program in e 2 prom figure 16.4-4 shows the operation of the address match detection function at storing the patch program in e 2 prom. figure 16.4-4 operation of address match detection function at storing patch program in e 2 prom 000000 h ffffff h program error detection address setting register patch program detection address setting (reset sequence) serial e 2 prom interface . patch program byte count . address for address detection . patch program e 2 prom (4) (2) (1) (3) rom ram (1) execution of detection address setting of reset sequence and normal program (2) branch to patch program which expanded in ram with int9 interrupt processing by address match detection (3) patch program execution by branching of int9 processing (4) execution of nomal program which branches from patch program .com .com .com .com 4 .com u datasheet
520 chapter 16 8/16 address match detection function flow of patch processing figure 16.4-5 shows the flow of patch processing using the address match detection function. figure 16.4-5 flow of patch processing reset read the 00 h of e 2 prom execution of patch program 000400 h to 000480 h branch to patch program jmp 000400 h end of patch program jmp ff8050 h enable address match detection (pacsr : ad0e = 1) e 2 prom : 0000 h = 0 program address = padr0 read detect address e 2 prom : 0001 h to 0003 h mcu : set to padr0 read patch program e 2 prom : 0010 h to 008f h mcu : 000400 h to 00047f h execution of normal program int9 int9 no yes no yes rom mb90387(s) program error detection address setting register stack area ram area patch program i/o area register/ram area ram ffffff h ff8050 h ff8000 h ff0000 h 000900 h 000480 h 000400 h 000100 h 000000 h e 2 prom patch program detect address (high) : ff h detect address (middle) : 80 h detect address (low) : 00 h patch program byte count : 80 h 0090 h 0010 h 0003 h 0002 h 0001 h 0000 h ffff h .com .com .com .com 4 .com u datasheet
521 chapter 16 8/16 address match detection function 16.5 program example of address match detection function this section gives a progr am example for the addr ess match detection function. program example for addr ess match detection function processing specifications if the address of the instruction to be executed by the program matches the address set in the detection address setting register (padr0), the int9 instruction is executed. coding example pacsr equ 00009eh ; address detection control register padrl equ 001ff0h ; detection address setting register 0 (low) padrm equ 001ff1h ; detection address setting register 0 (middle) padrh equ 001ff2h ; detection address setting register 0 (high) ; ;-----main program--------------------------------------------------------------- code cseg start: ; stack pointer (sp), etc., ; already reset mov padrl,#00h ; set address detection register 0 (low) mov padrm,#00h ; set address detection register 0 (middle) mov padrh,#00h ; set address detection register 0 (high) ; mov i:pacsr,#00000010b ; enable address match : processing by user : loop: : processing by user : bar loop ;-----interrupt program---------------------------------------------------------- wari: : processing by user : beti ; return from interrupt processing code ends ;-----vector setting------------------------------------------------------------- vect cseg abs=0ffh org 00ffdch dsl wari org 00ffdch ; set reset vector dsl start db 00h ; set to single-chip mode vect ends end start .com .com .com .com 4 .com u datasheet
522 chapter 16 8/16 address match detection function .com .com .com .com 4 .com u datasheet
523 chapter 17 rom mirroring function select module this chapter describes the functions and oper ations of the rom mirroring function select module. 17.1 overview of rom mirroring function select module 17.2 rom mirroring functi on select register (romm) .com .com .com .com 4 .com u datasheet
524 chapter 17 rom mirroring function select module 17.1 overview of rom mirroring function select module the rom mirroring function select module prov ides a setting so that rom data in the ff bank can be read by acc ess to the 00 bank. block diagram of rom mirror ing function se lect module figure 17.1-1 block diagram of rom mirroring function select module access to ff bank by rom mirroring function figure 17.1-2 shows the location in memory when rom mirroring function allows access to the 00 bank to read rom data in the ff bank. figure 17.1-2 access to ff bank by rom mirroring function address area rom ff bank 00 bank mi reserved reserved reserved reserved reserved reserved reserved address rom mirroring function select register (romm) data internal data bus ffffff h ff4000 h ff0000 h feffff h 00ffff h 004000 h mb90f387/s mb90387/s fc0000 h mb90v495g rom mirror area 00 bank ff bank (rom mirror-target area) .com .com .com .com 4 .com u datasheet
525 chapter 17 rom mirroring function select module memory space when rom mirror ing function enab led/disabled figure 17.1-3 shows the av ailability of access to memory space when the rom mirroring function is enabled or disabled. figure 17.1-3 memory space when rom mirroring function enabled/disabled (in single chip mode) list of registers and r eset values of rom mirror ing function select module figure 17.1-4 list of registers and reset values of rom mirroring function select module product type mb90v495g mb90f387/s mb90387/s address 1 001900 h 000900 h 000900 h rom area ff0000 h address 1 010000 h ffffff h 004000 h 003900 h 000100 h 0000c0 h 000000 h rom area ram area rom area ram area i/o area i/o area extend i/o area extend i/o area when rom mirroring function disabled when rom mirroring function enabled : when the area from "fe0000 h " to "feffff h " of mb90387/s or mb90f387/s is read out, the area "ff0000 h " to "ffffff h " can be read. fe0000 h rom area* rom area* : internal access memory : access disabled x: undefined bit151413121110 9 8 rom mirroring function select register (romm) xxxxxxx1 .com .com .com .com 4 .com u datasheet
526 chapter 17 rom mirroring function select module 17.2 rom mirroring function select register (romm) the rom mirroring function select register (romm) enables or disables the rom mirroring function. when the rom mirroring function is enab led, rom data in the ff bank can be read by access to the 00 bank. rom mirror function sel ect register (romm) figure 17.2-1 rom mirroring function select register (romm) reset value xxxxxxx1 b 12 13 11 10 9 8 15 14 ? ? ? ? ? ? w ? mi 0 1 rom mirroring function select bit rom mirroring function disabled rom mirroring function enabled bit 8 w : write only x : undefined ? : unused : reset value table 17.2-1 functions of rom mirroring function select register (romm) bit name function bit 8 mi: rom mirroring function select bit this bit enables or disables the rom mirroring function. when set to 0: disables rom mirroring function when set to 1: enables rom mirroring function when the rom mirroring function is enabled (mi = 1), data at rom addresses "ff4000 h " to "ffffff h " can be read by accessing addresses "004000 h " to "00ffff h " bit 9 to bit 15 unused bits read: value undefined be sure to set these bits to 0. note: while the rom area at addresses "004000 h " to "00ffff h " is being used, access to the rom mirroring function select register (romm) is prohibited. .com .com .com .com 4 .com u datasheet
527 chapter 18 512 kbit flash memory this chapter describes t he function and operation of 512 kbit flash memory. 18.1 overview of 512 kbit flash memory 18.2 registers and sector configuration of flash memory 18.3 flash memory control status register (fmcs) 18.4 how to start automatic algorithm of flash memory 18.5 check the execution state of automatic algorithm 18.6 details of programming/erasing flash memory 18.7 program example of 512 kbit flash memory .com .com .com .com 4 .com u datasheet
528 chapter 18 512 kbit flash memory 18.1 overview of 512 kbit flash memory there are three ways of programming and erasing flash memory as follows: 1. programming and eras ing using parallel writer 2. programming and eras ing using serial writer 3. programming and erasi ng by executing program this chapter describes the above "3. progr amming and erasing by executing program". overview of 512 kbit flash memory 512 kbit flash memory is placed in the ff h banks on the cpu memory map. the function of the flash memory i/f circuit provides read access and pr ogram access from the cpu to flash memory. programming and erasing flash memory are enabled by an instruction fr om the cpu via the flash memory i/f circuit. this allows reprogramming in the mounted state under cpu control and improvement of programming data efficiency. features of 512 kbit flash memory 128 kwords x 8 bits/64 kwords x 16 bits (16 k + 8 k + 8 k + 32 k) sector configuration uses automatic program algorithm (embedded algorithm tm : the same manner as mbm29lv200 erase pause/restart function detects completion of writing/erasing usin g data polling or toggle bit functions detects completion of writing/erasing by cpu interrupts sector erase function (any combination of sectors) programming/erase count 10,000 (min.) flash read cycle time (min.): 2 machine cycles sector protection function temporary sector prot ection cancel function extend sector protection function embedded algorithm tm is a registered trademark of advanced micro devices, inc. programming and erasing flash memory programming and erasing flash memory cannot be performed at one time. programming or erasing flash memory can be pe rformed by copying the program in flash memory to ram and executing the program copied in ram. note: the function for reading the manufacture code and device code is unprovided. these codes cannot be accessed by any command. .com .com .com .com 4 .com u datasheet
529 chapter 18 512 kbit flash memory 18.2 registers and sector configuration of flash memory this section explains the registers and t he sector configuratio n of flash memory. list of registers and r eset values of flash memory figure 18.2-1 list of registers and reset values of flash memory sector configuration of 512 kbit flash memory figure 18.2-2 shows the sector configuration of 512 kbit flash memory. the upper and lower addresses of each sector are give n in the figure. sector configuration for access from the cpu, the ff bank register has sa0 to sa3. figure 18.2-2 sector configuration of 512 kbit flash memory x: undefined bit76543210 flash memory control status register (fmcs) 000x0000 ff0000 h ff7fff h ff8000 h ff9fff h ffa000 h ffbfff h ffc000 h ffffff h cpu address 70000 h 77fff h 78000 h 79fff h 7a000 h 7bfff h 7c000 h 7ffff h writer address* sa3 (16 kbytes) flash memory sa0 (32 kbytes) sa1 (8 kbytes) sa2 (8 kbytes) *: the writer address is equivalent to the cpu address when data is programmed to flash memory by a parallel writer. this address is where programming and erasing are performed by a general- purpose writer. .com .com .com .com 4 .com u datasheet
530 chapter 18 512 kbit flash memory 18.3 flash memory control status register (fmcs) the flash memory control status register (fmc s) functions are shown in figure 18.3-1. flash memory control status register (fmcs) figure 18.3-1 flash memory control status register (fmcs) reset value 000x0000 b 4 53210 7 6 w w w r r/w r/w w r/w bit 2 reserved 0 reserved bit always set to "0" reserved 0 reserved bit always set to "0" bit 3 rdy 0 1 flash memory programming/erasing status bit programming/erasing (next data programming/erasing disabled) programming/erasing terminated (next data programming/erasing enabled) bit 4 we 0 1 flash memory programming/erasing enable bit programming/erasing flash memory area disabled programming/erasing flash memory area enabled bit 5 0 1 flash memory operation flag bit programming/erasing programming/erasing terminated bit 6 inte 0 1 flash memory programming/erasing interrupt enable bit interrupt disabled at end of programming/erasing interrupt enabled at end of programming/erasing bit 7 rdyint this rdyin bit cleared no effect r/w : read/write r : read only w : write only x : undefined : reset value read write bit 1 reserved 0 reserved bit always set to "0" bit 0 reserved 0 reserved bit always set to "0" .com .com .com .com 4 .com u datasheet
531 chapter 18 512 kbit flash memory table 18.3-1 functions of flash memory control status register (fmcs) bit name function bit 0 to bit 3 reserved: reserved bits always set these bits to 0. bit 4 rdy: flash memory programming/erasing status bit this bit shows the programming/erasing status of flash memory. if the rdy bit is 0, programming/erasing flash memory is disabled. the suspend commands, such as the read/reset command and sector erasing pause, can be accepted even if the rdy bit is 0. the rdy bit is set to 1 when programming/erasing is completed. bit 5 we: flash memory programming/erasing enable bit this bit enables or disables the prog ramming/erasing of flash memory area. the we bit should be set before star ting the command to program/erase flash memory. when set to 0: no program/erase signal is generated even if the command to program/erase the ff bank is input. when set to 1: programming/erasing flash memory is enabled after inputting program/erase command to the ff bank. when not performing programming/erasing, the we bit should be set to 0 so as not to accidentally pr ogram or erase flash memory. bit 6 rdyint: flash memory operation flag bit this bit shows the operati ng state of flash memory. if programming/erasing flash memory is terminated, the rdyint bit is set to 1 in timing of termination of the automatic flash memory algorithm. if the rdyint bit is set to 1 when an interrupt as programming/erasing flash memory is terminated is enabled (fmcs: inte = 1), an interrupt is requested. if the rdyint bit is 0, programming/erasing flash memory is disabled. when set to 0: cleared. when set to 1: unaffected. if the read-modify-write (rmw) instru ctions are used, 1 is always read. bit 7 inte: flash memory programming/erasing interrupt enable bit this bit enables or disables an interrupt as programming/erasing flash memory is terminated. when set to 1: if the flash memory operation flag bit is set to 1 (fmcs: rdyint = 1), an interrupt is requested. .com .com .com .com 4 .com u datasheet
532 chapter 18 512 kbit flash memory note: the flash memory operation flag bit (rdyint) and flash memory programming/erasing status bit (rdy) do not change simultaneously. a program should be created so that either rd yint bit or rdy bit can identify the termination of programming/erasing. automatic algorithm end timing rdy bit rdyint bit 1 machine cycle .com .com .com .com 4 .com u datasheet
533 chapter 18 512 kbit flash memory 18.4 how to start automatic algorithm of flash memory there are four commands for st arting the automatic algorit hm of flash memory: read/ reset, write, chip er ase. the sector erase com mand controls suspension and resumption of sector erase. command sequence table table 18.4-1 list the commands used in programming/erasing flash memory. all data is written to command registers by byte acce ss but should be written by word access in the normal mode. upper data bytes are ignored. table 18.4-1 command sequence table notes: addresses in the table are the values in th e cpu memory map. all addresses and data are hexadecimal values, where "x" is any value. ra: read address pa: program address. only even addresses can be specified. sa: sector address (see "18.2 registers and sector configuration of flash memory") rd: read data pd: program data. only word data can be specified. *: two kinds of read/reset commands can reset flash memory to the read mode. write cycle of first bus write cycle of second bus write cycle of third bus write cycle of fourth bus write cycle of fifth bus write cycle of sixth bus address data data data data data data address address address (even) (word) address address command sequence read/ reset* read/ reset* write program chip erase auto select sector erase suspend sector erase resume input of address"ffxxxx"data (xxb0 h ) suspends sector erasing. input address"ffxxxx"data (xx30 h ) suspends and resume sector erasing. bus write access 1 4 4 6 6 3 ffxxxx ffaaaa ffaaaa ffaaaa ffaaaa ffaaaa xxf0 xxaa xxaa xxaa xxaa xxaa ? xx55 xx55 xx55 xx55 xx55 ? xxf0 xxa0 xx80 xx80 xx90 ? rd pd xxaa xxaa ? ? ? ? xx55 xx55 ? ? ? ? xx10 xx30 ? ? ff5554 ff5554 ff5554 ff5554 ff5554 ? ffaaaa ffaaaa ffaaaa ffaaaa ffaaaa ? ra pa ffaaaa ffaaaa ? ? ? ? ff5554 ff5554 ? ? ? ? ffaaaa sa ? sector erase (even) .com .com .com .com 4 .com u datasheet
534 chapter 18 512 kbit flash memory auto select in table 18.4-2 is th e command to check the state of sector protection. the addresses must be set as indicated below together with the command in table 18.4-2. table 18.4-2 address setting for auto select aq13 to aq15 aq7 aq2 aq1 aq0 dq7 to dq0 sector protection sector address l h l l code * *: the output at the protect ed sector address is "01 h ". the output at the unprotected sector address is "00 h ". .com .com .com .com 4 .com u datasheet
535 chapter 18 512 kbit flash memory 18.5 check the execution state of automatic algorithm since the programming/erasing flow is controlled by the automatic al gorithm, hardware sequence can check the internal oper ating state of flash memory. hardware sequence flags overview of hardware sequence flag the hardware sequence flag consists of the following 5-bit outputs: data polling flag (dq7) toggle bit flag (dq6) timing limit over flag (dq5) sector erasing timer flag (dq3) toggle bit 2 flag (dq2) these flags can be used to check wh ether programming, chip and sector er asing, and erase code writing are enabled. the hardware sequence flags can be referred by set ting command sequences and performing read access to the address of a target sector in flash memory. ta ble 18.5-1 gives the bit allocation of the hardware sequence flags. to identify whether automatic programming/chip and sector erasing is in ex ecution or terminated, check the hardware sequence flag or the flash memory pr ogramming/erasing status bit in the flash memory control status register (f mcs: rdy). programming/erasing is te rminated, returning to the read/reset state. to create a programming/erasing program, use the dq 7, dq6, dq5, dq3 and dq2 flags to check that automatic programming/erasing is terminated and read data. the hardware sequence flags can also be used to check whether the second and later sector erase code writing is enabled. table 18.5-1 bit allocation of hardware sequence flags bit no. 76543210 hardware sequence flag dq7 dq6 dq5 ? dq3 dq2 ?? .com .com .com .com 4 .com u datasheet
536 chapter 18 512 kbit flash memory explanation of hardware sequence flag table 18.5-2 lists the functions of the hardware sequence flag. table 18.5-2 list of hardware sequence flag functions state dq7 dq6 dq5 dq3 dq2 state change in normal operation programming --> completed (when program address specified) dq7 --> data:7 toggle --> data:6 0 --> data:5 0 --> data:3 1 --> data:2 chip and sector erasing --> completed 0 --> 1 toggle --> stop 0 --> 11 toggle --> stop sector erasing wait --> started 0 toggle 0 0 --> 1 toggle erasing --> sector erasing suspended (sector being erased) 0 --> 1 toggle --> 1 01 --> 0 toggle sector erasing suspended --> resumed (sector being erased) 1 --> 01 --> toggle 0 0 --> 1 toggle sector erasing being suspended (sector not being erased) data:7 data:6 data:5 data:3 data:2 abnormal operation programming dq7 toggle 1 0 1 chip and sector erasing 0 toggle 1 1 * *: if the dq5 flag is 1 (timing limit over), the dq2 flag performs the toggle operation for continuous reading from the programming/erasing sector but does not perform th e toggle operation for read ing from other sectors. .com .com .com .com 4 .com u datasheet
537 chapter 18 512 kbit flash memory 18.5.1 data polling flag (dq7) the data polling flag (dq7) is mainly used to notify that the auto matic algorithm is executing or has been completed us ing the data polling function. data polling flag (dq7) table 18.5-3 and table 18.5-4 give the state transition of the data polling flag. at programming read access during execution of the auto-programmi ng algorithm causes flash memory to output the reversed data of bit 7 last written. read access at the end of the auto -programming algorithm causes flash memory to output the value of bit 7 at the address to which read access was performed. at chip/sector erasing during executing chip and sector er asing algorithms, when read access is made to the currently being erasing sector, bit 7 of flash memory outputs 0. when chip erasing/sector erasing is terminated, bit 7 of flash memory outputs 1. table 18.5-3 state transition of data polling flag (state change at normal operation) operating state programming --> completed chip and sector erasing --> completed wait for sector erasing --> started sector erasing --> erasing suspended (sector being erased) sector erasing suspended --> resume (sector being erased) sector erasing being suspended (sector not being erased) dq7 dq7 --> data :7 0 --> 1 0 0 --> 1 1 --> 0 data:7 table 18.5-4 state transition of data polling flag (state change at abnormal operation) operating state programming chip and sector erasing dq7 dq7 0 .com .com .com .com 4 .com u datasheet
538 chapter 18 512 kbit flash memory at sector erasing suspension read access during sector erasing suspension causes fl ash memory to output 1 if the address specified by the address signal belongs to the sector being er ased. flash memory outputs bit 7 (data: 7) of the read value at the address specified by the signal address if the addr ess specified by the address signal does not belong to the sector being erased. referring this flag together with the toggle bit flag (dq6) permits a decision on whether flash memory is in the erase suspended state an d which sector is being erased. note: read access to the specified address while the auto matic algorithm starts is ig nored. data reading is enabled after 1 is set to the data polling flag (dq7). data reading after the end of the automatic algorithm should be performed following read access afte r completion of data polling has been checked. .com .com .com .com 4 .com u datasheet
539 chapter 18 512 kbit flash memory 18.5.2 toggle bit flag (dq6) the toggle bit flag (dq6) is a hardware sequence flag used to notify that the automatic algorithm is being executed or in the end state using the toggle bit function. toggle bit flag (dq6) table 18.5-5 and table 18.5-6 give the state transition of the toggle bit flag. at programming and chip/sector erasing if a continuous read access is made during the execution of the automati c algorithm for programming and chip erasing/sector erasing, flash memory toggle-outputs 1 and 0 alternately every reading. if a continuous read access is made after the co mpletion of the automatic algorithm for programming and chip erasing/sector erasing, flash memory outputs bit 6 (data: 6) for the read value of the read address every reading. at sector erasing suspension if a read access is made in the sector erasing susp ension state, flash memory outputs 1 when the read address is the sector being erased an d bit 6 (data: 6) for the read valu e of the read address when the read address is not the sector being erased. table 18.5-5 state transition of toggle bit flag (state change at normal operation) operating state programming --> completed chip and sector erasing --> erasing completed wait for sector erasing --> erasing started sector erasing --> erasing suspended (sector being erased) sector erasing suspended --> resume (sector being erased) sector erasing suspended (sector not being erased) dq6 toggle --> data :6 toggle --> stop toggle toggle --> 1 1 --> toggle data:6 table 18.5-6 state transition of toggle bit flag (state change at abnormal operation) operating state programming chip and sector erasing dq6 toggle toggle reference: if the sector for programming is reprogram-protected, the toggle bit flag (dq6) produces a toggle output for approximately 2 s, and then termin ates it without reprogramming data. if all sectors for er asing are reprogram-protected , the toggle bit flag (dq6) produces a toggle output for approximately 100 s, and then returns to the read/reset state without reprogramming data. .com .com .com .com 4 .com u datasheet
540 chapter 18 512 kbit flash memory 18.5.3 timing limit over flag (dq5) the timing limit over flag (dq5) is a hardw are sequence flag that not ifies flash memory that the execution of the au tomatic algorithm has exceeded a prescribed time (the time required for programming/erasing). timing limit over flag (dq5) table 18.5-7 and table 18.5-8 give the state transition of the timing limit over flag. at programming and chip erasing/sector erasing if a read access made after starting the automati c algorithm for programming or chip erasing/sector erasing is within a prescribed time (the time required for programming/erasing), the timing limit over flag (dq5) outputs 0. if it exceeds the prescribed time, the timing limit ov er flag (dq5) outputs 1. the timing limit over flag (dq5) can be used to identify the success or failure of programming/erasing, regardless of whether the automatic algorithm is in progress or terminated. if the automatic algorithm by the data polling or the toggle bit function is in execution when the timing limit over flag (dq5) outputs 1, programming can be identified as a failure. for example, when 1 is set to th e flash memory address with 1 set the flash memory, programming fails. in this case, the flash memory will be locked and th e automatic algorithm will not complete. therefore, no valid data is output from the data polling flag (dq7). also, the toggle bit flag (dq6) does not stop the toggle operation and exceeds the time limit, causing the timing limit over flag (dq5) to output 1. this state means that the flash memory is not bein g used correctly; it does not mean that the flash memory is faulty. when this st ate occurs, execute the reset command. table 18.5-7 state transition of timing limit over flag (state change at normal operation) operating state programming --> completed chip and sector erasing --> completed wait for sector erasing --> started sector erasing --> erasing suspended (sector being erased) sector erasing suspended --> resume (sector being erased) sector erasing being suspended (sector not being erased) dq5 0 --> data :5 0 --> 1000data :5 table 18.5-8 state transition of timing limit over flag (state change at abnormal operation) operating state programming chip and sector erasing dq5 1 1 .com .com .com .com 4 .com u datasheet
541 chapter 18 512 kbit flash memory 18.5.4 sector erase timer flag (dq3) the sector erase timer flag (dq3) is a hardw are sequence flag used to notify during the period of waiting for sector erasing af ter the sector eras e command has started. sector erase timer flag (dq3) table 18.5-9 and table 18.5-10 give the state transition of the sect or erase timer flag. at sector erasing if a read access made after starting the sector erase co mmand is within a sector erasing wait period, the sector erasing timer flag (dq3) outputs 0. if it exceeds the period, the sector erasing timer flag (dq3) outputs 1. if the sector erasing timer flag ( dq3) is 1, indicating th at the automatic algorith m for sector erasing by the data polling or toggle bit function is in prog ress (dq = 0; dq6 produces a toggle output), sector erasing is performed. if any command other than the s ector erasing suspension is set, it is ignored until sector erasing is terminated. if the sector erasing timer flag (dq3) is 0, flash memory can accep t the sector erase command. to program the sector erase command, check that the sector erasing timer flag (dq3) is 0. if the flag is 1, flash memory may not accept the sect or erase command of suspending. at sector erasing suspension read access during sector erasing su spension causes flash memory to output 1, if the read address is the sector being erased. flash memory outputs bit 3 (d ata: 3) for the read valu e of the read address when the read address is not the sector being erased. table 18.5-9 state transition of sector erase timer flag (state change at normal operation) operating state programming --> completed chip and sector erasing --> completed wait for sector erasing --> started sector erasing --> erasing suspended (sector being erased) sector erasing suspended --> resume (sector being erased) sector erasing being suspended (sector not being erased) dq3 0 --> data:3 1 0 --> 11 --> 00 --> 1data:3 table 18.5-10 state transition of sector erase timer flag (state change at abnormal operation) operating state programming chip and sector erasing dq3 0 1 .com .com .com .com 4 .com u datasheet
542 chapter 18 512 kbit flash memory 18.5.5 toggle bit 2 flag (dq2) the toggle bit 2 flag (dq2) is a hardware sequence flag that notifi es flash memory that sector erasing is being suspended using the toggle bit function. toggle bit flag (dq2) table 18.5-11 and table 18.5-12 give the state transition of the toggle bit flag. at sector erasing if a continuous read access is made during the execution of the automa tic algorithm for chip erasing/ sector erasing, flash memory toggle-out puts 1 and 0 alternately every reading. if a continuous read access is made after the completion of the algorithm for chip erasing/sector erasing, flash memory outputs bit 2 (data: 2) for the r ead value of the read address every reading. table 18.5-11 state transition of toggle bit flag (state change at normal operation) operating state programming --> completed chip and sector erasing --> completed wait for sector erasing --> started sector erasing --> erasing suspended (sector being erased) sector erasing suspended --> resume sector being erased) sector erasing being suspended (sector not being erased) dq2 1 --> data :2 toggle --> stop toggle toggle toggle data :2 table 18.5-12 state transition of toggle bit flag (state change at abnormal operation) operating state programming chip and sector erasing dq2 1 * *: if the dq5 flag is 1 (timing limit over), the dq2 flag performs the toggle operation for continuous reading from the programm ing/erasing sector but does not perform the toggle operation for reading from other sectors. .com .com .com .com 4 .com u datasheet
543 chapter 18 512 kbit flash memory at sector erasing suspension if a read access is made in the sector erasing suspen sion state, flash memory outputs 1 and 0 alternately when the read address is the sector being erased and bit 2 (data: 2) for th e read value of the read address when the read address is not the sector being erased. if programming is performed in th e sector erasing suspension state, flash memory outputs 1 when a continuous read access is started with the sector that is not in the erasing suspension state. the toggle bit 2 flag (dq2) is used together with the toggle bit flag (dq6) to detect that sector erasing is suspended (the dq2 flag performs the toggle operation but the dq6 flag does not). if a read access from the sector be ing erased is made, the toggle bi t 2 flag (dq2) pe rforms the toggle operation, so it can also be used to detect the sector being erased. reference: if all sectors for erasing are reprogram-protected , the toggle bit flag (dq2) produces a toggle output for approximately 100 s, and then returns to the read/reset state without reprogramming data. .com .com .com .com 4 .com u datasheet
544 chapter 18 512 kbit flash memory 18.6 details of programming/erasing flash memory this section explains the procedure for inputting co mmands starting the automatic algorithm, and for read/reset of flash me mory, programming, ch ip erasing, sector erasing, sector erasing suspension and sector er asing resumption. detailed explanation of pr ogramming and erasing flash memory automatic algorithm can be started by programming the command sequence of read/reset, programming, chip erasing, sector eras ing, sector erasing suspen sion and erasing resumption from cpu to flash memory. programming flash memory from the cpu should always be performed continuously. the termination of the automatic algorithm can be checked by the data pollin g function. after normal termination, it returns to the read/reset state. each operation is explaine d in the following order. read/reset state data programming all data erasing (chip all erase) any data erasing (sector erase) sector erasing suspension sector erasing resumption .com .com .com .com 4 .com u datasheet
545 chapter 18 512 kbit flash memory 18.6.1 read/reset state in flash memory this section explains the procedure for input ting the read/reset co mmand to place flash memory in the read/reset state. read/reset state in flash memory flash memory can be placed in the read/reset state by c ontinuously tran smitting the read/reset command in the command sequence table from cpu to flash memory. there are two kinds of read/reset commands: one is executed at one time bus operation, and the other is executed at three times bus oper ations; the command sequence of both is essentially the same. since the read/reset state is the init ial state for flash memory, flash memo ry always enters this state after power-on and at the normal termination of command. the read/reset state is also described as the wait state for command input. in the read/reset state, a read access to flash memory enables data to be read. as is the case with mask rom, a program access from the cpu can be made. a read access to flash memory does not require the read/reset command. if the command is not terminated nor mally, use the read/reset command to initialize the automatic algorithm. .com .com .com .com 4 .com u datasheet
546 chapter 18 512 kbit flash memory 18.6.2 data programming to flash memory this section explains the procedure for inputting t he program command to program data to flash memory. data programming to flash memory in order to start the data programming automatic algorithm, continuously transmit the program command in the command sequence ta ble from cpu to flash memory. at completion of data programming to a target addr ess in the fourth cycle, the automatic algorithm starts automatic programming. how to specify address the only even addresses can be specified for the programming addr ess specified by programming data cycle. specifying odd addresses prev ents correct writing. writing to even addresses must be performed in word data units. programming is possible in any address order or ev en beyond sector boundaries. however, execution of one programming command, permits programming of only one word for data. notes on data programming data 0 cannot be returned to data 1 by programming. when data 0 is programmed to data 1, the data polling algorithm (dq7) or toggling (dq6) is not terminated and the flash memory is considered faulty; the timing limit over flag (dq5) is determined as an error. when data is read in the read/reset state, the bit data remains 0. to return the bit data to 1 from 0, erase flash memory data. all commands are ignored during automatic prog ramming. if a hardware reset occurs during programming, data being programmed to addresses are not assured. data programming procedure figure 18.6-1 gives an example of the procedur e for programming data into flash memory. the hardware sequence flags can be used to check the operating state of the automatic algorithm in flash memory. the data polling flag (dq7) is used fo r checking the completion of programming to flash memory in this example. flag check data should be read from th e address where data was last written. because the data polling flag (dq7) and the timing limit over flag (dq5) change at the same time, the data polling flag (dq7) must be checked even when the timing limit over flag (dq5) is 1. similarly, since the toggle bit flag (dq6) stops toggling at the same time the timing limit over flag (dq5) changes to 1, toggle bi t flag (dq6) mu st be checked. .com .com .com .com 4 .com u datasheet
547 chapter 18 512 kbit flash memory figure 18.6-1 example of data programming procedure start internal address read program command sequence (1) ffaaaa xxaa (2) ff5554 xx55 (3) ffaaaa xxa0 (4) program address program data next address internal address read fmcs : we (bit 5) programming enabled data polling (dq7) data polling (dq7) data data timing limit (dq5) 1 completed 0 last address yes no fmcs : we (bit 5) programming enabled programming error data data check by hardware sequence flag .com .com .com .com 4 .com u datasheet
548 chapter 18 512 kbit flash memory 18.6.3 data erase from fl ash memory (chip erase) this section explains the procedure for inputting the chip erase comm and to erase all data from flash memory. all data erase from fl ash memory (chip erase) all data can be erased from flash memory by continuously transmitting the chip erase command in the command sequence table from cpu to flash memory. the chip erase command is executed in six bus operatio ns. chip erasing is started at completion of the sixth programming cycle. before chip erasing, the user need not perform pr ogramming to flash memory. during execution of the automatic erasing algorithm, flash memory auto matically programs 0 befo re erasing all cells. .com .com .com .com 4 .com u datasheet
549 chapter 18 512 kbit flash memory 18.6.4 erasing any data in flash memory (sector erasing) this section explains the procedure for inputting t he sector erase command to erase any data in flash memory. sector-by-sector erasing is enabled and multiple sectors can be specified at a time. erasing any data in flash memory (sector erasing) any sector in flash memory can be erased by cont inuously transmitting the s ector erase command in the command sequence table from cpu to flash memory. how to specify sector the sector erase command is executed in six bus operations. by setting the address on the sixth cycle in the even address in the target sector and programming the sector erase code (30 h ) to data, a 50 s sector erasing wait is started when erasing more than one sect or, the sector erase code (30 h ) is programmed to the sector address to be erased, following the above. notes on specifying multiple sectors sector erasing is started after a 50 s period waiting for sector erasing is completed after the last sector erase code has been programmed. that is, when erasing more than one sector simulta neously, the address of erase sector and the sector erase code must be input within 50 s. if the sector er ase code is input 50 s or later, it cannot be accepted. whether continuous programming of the sector erase code is enabled can be checked by the sector erase timer flag (dq3). in this case, the address from which the sector er ase timer is flag (dq3) read should correspond to the sector to be erased. erasing procedure for flash memory sectors the state of the automatic algorithm in the flash memory can be determined using the hardware sequence flag. figure 18.6-2 gives an example of the flash memory s ector erase procedure. in this example, the toggle bit flag (dq6) is used to check that erase ends. dq6 terminates toggling concurrently with the change of the timing limit over flag (dq5) to 1, so the dq6 must be checked even when dq5 is 1. similarly, the data polling flag (dq7) changes concurrently with the transition of the dq5, so dq7 must be checked. .com .com .com .com 4 .com u datasheet
550 chapter 18 512 kbit flash memory figure 18.6-2 example of sector erasing procedure start (6) code input to erase sector (30 h ) erase command sequence (1) ffaaaa xxaa (2) ff5554 xx55 (3) ffaaaa xx80 (4) ffaaaa xxaa (5) ff5554 xx55 next sector internal address read internal address read fmcs : we (bit 5) erasing enabled is any other erase sector? timing limit (dq5) 1 completed 0 last sector fmcs : we (bit 5) erasing enabled erasing error check by hardware sequence flag internal address read 2 internal address read 1 toggle bit (dq6) data 1 = data 2 toggle bit (dq6) data 1 = data 2 no no no no yes yes yes yes sector erase completed? no yes .com .com .com .com 4 .com u datasheet
551 chapter 18 512 kbit flash memory 18.6.5 sector erase suspension in flash memory this section explains the procedure for inputting the sec tor erase suspend command to suspend sector erasing. da ta can be read from t he sector not being erased. sector erase suspension in flash memory to cause flash memory sector erasing to suspend, continuously transmit th e sector erasing suspend command in the command sequence ta ble from cpu to flash memory. the sector erasing suspe nd command suspends the sector erase cu rrently being performed, enabling data read from a sector that is curren tly not being erased. only read can be performed when this command is suspended; programming cannot be performed. this command is only enabled during the sector eras ing period including the erasing wait time; it is ignored during the chip erasing period or during programming. the sector erasing suspend command is execut ed when the sector erasing suspend code (b0 h ) is programmed. arbitrary address in flash memory should be set for address. if the sector erasing suspend command is executed during sector erasing pa use, the command inpu t again is ignored. when the sector erasing suspend command is input during the sector erasing wait period, the sector erase wait state ends immediately, the erasing is interrupted, a nd the erase stop state occurs. when the erase suspend command is input during the sector erasing after the sector erase wait period, the erase suspend state occurs after 15 s max. .com .com .com .com 4 .com u datasheet
552 chapter 18 512 kbit flash memory 18.6.6 sector erase resumption in flash memory this section explains the procedure for inputting the sector erase r esume command to resume erasing of the suspended flash memory sector. erase resumption in flash memory suspended sector erasing can be resumed by c ontinuously transmitting the sector erase resume command in the command sequence ta ble from cpu to flash memory. the sector erase resume command resumes sector erasing suspended by the sector erase suspend command. this command is executed by writing the erase resume code (30 h ). in this case, any address in the flash memory area is specified. inputting the sector erase resume comma nd during sector erasing is ignored. .com .com .com .com 4 .com u datasheet
553 chapter 18 512 kbit flash memory 18.7 program example of 512 kbit flash memory a program example of the 512 kb it flash memory is given below. program example of 5 12 kbit flash memory name flashwe title flashwe ;-------------------------------------------------------------------------------- ; 512 kbit flash sample program ; 1: transfer program in flash (address ffbc00 h, ; sector sa2) to ram (address 000700h). ; 2: execute program on ram. ; 3: program pdr1 value to flash (address ff0000h, sector sa0). ; 4: read programmed value (address ff0000h, sector sa0) and output to pdr2. ; 5: erase programmed sector (sa0). ; 6 : output check that data is erased. ; conditions ; - count of bytes transferred to ram: 100h (25 6 bytes) ; - completion of programming and erasing checked by: ; timing limit over flag (dq5) ; toggle bit flag (dq 6 ) ; rdy (fmcs) ; - action taken at error ; output h to p00 to p07. ; issue reset command. ;-------------------------------------------------------------------------------- ; resous ioseg abs=00 ; definition of "resous" i/o segment org 0000h pdr0 rb 1 pdr1 rb 1 pdr2 rb 1 pdr3 rb 1 org 0010h ddr0 rb 1 ddr1 rb 1 ddr2 rb 1 ddr3 rb 1 org 00a1h ckscr rb 1 org 00aeh fmcs rb 1 org 00 6 fh romm rb 1 resous ends ; .com .com .com .com 4 .com u datasheet
554 chapter 18 512 kbit flash memory ssta sseg rw 0127h sta_t rw 1 ssta ends ; data dseg abs=0ffh ; flash command address org 5554h comadr2 org 1 org 0aaaah comadr1 org 1 data ends ;-------------------------------------------------------------------------------- ; main program (sa1) ;-------------------------------------------------------------------------------- code cseg start: ;------------------------------------------------------------------------ ; initialize ;------------------------------------------------------------------------ mov ckscr,#0bah ; set to 3-multiplying count mov rp,#0 mov a,#!sta_t mov ssb,a movw a,#sta_t movw sp, a mov romm,#00h ; mirror off mov pdro,#00h ; for error check mov ddr0,#0ffh mov pdr1,#00h ; data input port mov ddr1,#00h mov pdr2,#00h ; data output port mov ddr2,#0ffh ;------------------------------------------------------------------------ ; transfer flash programming/erasing program (ffbc00h) to ram ; (address 700h) ;------------------------------------------------------------------------ movw a,#0700h ; transfer destination ram area movw a,#0bc00h ; transfer source address ; (position where program exist) movw rw0,#100h ; count of bytes to be transferred movs adb,pcb ; transfer 100h from ffbc00h to 000700h callp 000700h ; jump to address where transferred program exists ;------------------------------------------------------------------------ ; data output ;------------------------------------------------------------------------ out mov a,#0ffh mov adb,a movw rw2,#0000h movw a,@rw2+00 mov pdr2,a end jmp * code ends .com .com .com .com 4 .com u datasheet
555 chapter 18 512 kbit flash memory ;-------------------------------------------------------------------------------- flash programming/erasing program (sa2) ;-------------------------------------------------------------------------------- ramprg cseg abs=0ffh org 0bc00h ;------------------------------------------------------------------------ ; initialize ;------------------------------------------------------------------------ movw rw0,#0500h ; rw0: ram space for storage of input data ; 00:0500 to movw rw2,#0000h ; rw2: flash memory programming address ; fd:0000 to mov a,#00h ; dtb change mov dtb,a ; specify bank for @rw0 mov a,#0ffh ; adb change 1 mov adb,a ; specify bank for program mode specifying address mov pdr3,#00h ; initialize switch mov ddr3,#00h ; wait1 bbc pdr3:0,wait1 ; pdr3: 0 with high level, start programming ; ;-------------------------------------------------------------------------------- ; program (sa0) ;-------------------------------------------------------------------------------- mov a,pdr1 movw @rw0+00,a ; save pdr1 data in ram. mov fmcs,#20h ; set program mode. movw adb:comadr1, #00aah ; flash program command 1 movw adb:comadr2, #0055h ; flash program command 2 movw adb:comadr1, #00a0h ; flash program command 3 ; movw a, @rw0+00 ; program input data (rw0) to flash memory (rw2). ; movw @rw2+00, a write ; waiting time check ;------------------------------------------------------------------------ ;error occurs when the time limit over check flag is set and toggling. ;------------------------------------------------------------------------ movw a,@rw2+00 and a,#20h ; dq5 time limit check bz ntow ; time limit over movw a,@rw2+00 ; ah movw a,@rw2+00 ; al xorw a ; xor of ah and al (1 if value is invalid) and a,#40h ; is dq 6 toggle bit? bnz error ; if no, go to error. ;------------------------------------------------------------------------ ;programming end check (fmcs-rdy) ;------------------------------------------------------------------------ ntow movw a,fmcs and a,#10h ; extract rdy bit (bit 4) of fmcs. bz write ; is programming ended? mov fmcs,#00h ; cancel program mode. .com .com .com .com 4 .com u datasheet
556 chapter 18 512 kbit flash memory ;------------------------------------------------------------------------ ;program data output ;------------------------------------------------------------------------ movw rw2,#0000h ; output program data movw a, @rw2+00 mov pdr2,a ; wait2 bbc pdr3:1,wait2 ; pdr3:1 with "h", start sector erasing. ; ;-------------------------------------------------------------------------------- ; sector erasing (sa0) ;-------------------------------------------------------------------------------- mov @rw2+00,#0000h ; initialize address mov fmcs,#20h ; set erase mode movw adb:comadr1,#00aah ; flash command 1 movw adb:comadr2,#0055h ; flash command 2 movw adb:comadr1,#00 8 0h ; flash command 3 movw adb:comadr1,#00aah ; flash command 4 movw adb:comadr2,#0055h ; flash command 5 mov @rw2+00,#0030h ; issue erase command to sector to be erased 6 . els ; waiting time check ;------------------------------------------------------------------------ ;error occurs when time limit over check flag is set and toggling is underway. ;-------------------------------------------------------------------------------- movw a,@rw2+00 and a,#20h ; dq5 time limit check bz note ; time limit over movw a,@rw2+00 ; during ah programming, "h/l" is output movw a,@rw2+00 ; alternately every time al is read from dq 6 xorw a ; xor of ah and al (1 if dq 6 value invalid, ; indicating programming underway) and a, #40h ; is dq 6 toggle bit "h"? bnz error ; if "h", go to error ;------------------------------------------------------------------------ ;erasing end check (fmcs-rdy) ;------------------------------------------------------------------------ ntoe movw a,fmcs ; and a,#10h ; extract rdy bit (bit 4) of fmcs bz els ; is erasing ended? mov fmcs,#00h ; cancel flash erase mode retp ; return to main program ;-------------------------------------------------------------------------------- ;error ;-------------------------------------------------------------------------------- error mov adb:comadr1,#0f0h ; reset command (read enabled) mov fmcs,#00h ; cancel flash mode mov pdr0,#0ffh ; check error processing retp ; return to main program ramprg ends ;------------------------------------------------------------------- vect cseg abs=0ffh org 0ffdch dsl start db 00h vect ends ; ends start .com .com .com .com 4 .com u datasheet
557 chapter 19 flash serial programming connection this chapter describes an example of serial programming connection using t he flash microcontroller programmer made by yokogawa digital computer corporation. 19.1 basic configuration of serial programming connection for f 2 mc-16lx mb90f387/s 19.2 connection example in single-chip mode (user power supply) 19.3 connection example in single-chip mode (writer power supply) 19.4 example of minimum conn ection to flash microcontroller programmer (user power supply) 19.5 example of minimum conn ection to flash microcontroller programmer (writer power supply) .com .com .com .com 4 .com u datasheet
558 chapter 19 flash serial programming connection 19.1 basic configuration of seri al programming connection for f 2 mc-16lx mb90f387/s the mb90f387/s supports the serial on-board pr ogramming of flash rom (fujitsu standard). the specification for serial on- board programming are explained below. basic configuration of serial programming connection for mb90f387/s the flash microcontroller programmer made by yoko gawa digital computer corporation is used for fujitsu standard serial on-board programming. figure 19.1-1 basic configurati on of serial programming connection note: inquire of yokogawa digital computer corporatio n for details about the functions and operations of the af220/af210/af120/af110 flash microcontroller programmer, general-purpose common cable for connection (az210), and connectors flash microcontroller programmer + memory card mb90f387(s) user system rs232c host interface cable (az221) general-purpose common cable (az210) stand-alone operation enable clock synchronous serial table 19.1-1 pins used for fujitsu standard serial on-board programming (1/2) pin function supplementary information md2, md1, md0 mode pins writing 1 to md2, 1 to md1 and 0 to md0 sets the flash serial program mode. x0, x1 oscillation pins in the flash serial program mode, the internal operating clock of the cpu has a frequency one time that of the pll cl ock, so the internal operating clock frequency is the same as the oscillation clock frequency. since the oscillation clock frequency serves as an internal operation clock, the oscillator used for serial programming have frequencies from 1 mhz to 16 mhz. p30, p31 programming program start pins input a low level to p30 and a high level to p31. .com .com .com .com 4 .com u datasheet
559 chapter 19 flash serial programming connection figure 19.1-2 control circuit rst reset pin ? sin1 serial data input pin uart is used in clock synchronous mode. sot1 serial data output pin sck1 serial clock input pin c c pin this pin is a capacitance pin for stab ilizing voltage. connect the ceramic capacitor approx. 0.1 f externally. v cc power supply voltage pin if the program voltage (5 v 10%) is supplied from the user system, the flash microcontroller programmer need not be connected. v ss gnd pin gnd pin is common to the ground of th e flash microcontroller programmer. note: even if the p30, sin1, sot1, and sck1 pins are used for the user system, the controller shown in the figure below is required. the tics signal of th e flash microcontroller programmer can be used to disconnect the user circuit during serial programming. see the following serial programmi ng connection examples given in s ections "19.2 connection example in single-chip mode (user power supply)" to "19.5 example of minimum connection to flash microcontroller programmer (writer power supply)". connection example in single-chip mode (user power supply) connection example in single-chip mode (writer power supply) example of minimum connection with flash mi crocontroller programm er (user power supply) example of minimum connection with flash micr ocontroller programmer (writer power supply) table 19.1-1 pins used for fujitsu standard serial on-board programming (2/2) pin function supplementary information af220/af210/af120/af110 programming control pin mb90f387(s) programming control pin af220/af210/af120/af110 /tics pin user 10 k ? .com .com .com .com 4 .com u datasheet
560 chapter 19 flash serial programming connection oscillation clock frequency and serial clock input frequency the inputable serial clock frequency for the mb90f387 /s can be determined by the following expression. therefore, change the serial clock input frequency according to the sett ing of the programmer of the flash microcontroller on the basis of the oscillation clock frequency. inputable serial clock frequency = 0.125 x oscillation clock frequency flash microcontroller programmer system configuration (made by yokogawa digita l computer corporation) table 19.1-2 maximum serial clock frequency oscillation clock frequency maximum serial clock frequency that can be input for the microcomputer maximum serial clock frequency that can be set with af220/af210/ af120/af110 maximum serial clock frequency that can be set with af200 4 mhz 500 khz 500 khz 500 khz 8 mhz 1 mhz 850 khz 500 khz 16 mhz 2 mhz 1.25 mhz 500 khz table 19.1-3 flash microcontroller programmer system configuration (made by yokogawa digital computer corporation) model function unit af220/ac4p model with internal ethernet interface /100 v to 220 v power adapter af210/ac4p standard model /100 v to 220 v power adapter af120/ac4p single ke y internal ethernet interface model /100 v to 220 v power adapter af110/ac4p single key model /100 v to 220 v power adapter az221 pc/at rs232c cable for writer az220 standard target probe (a) length: 1 m ff201 control module for fujitsu f 2 mc-16lx flash microcontroller /p2 2mb pc card (option) flash memory corresponding max. 128 kb /p4 4mb pc card (option) flash memory corresponding max. 512 kb note: the af200 flash microcontroller programmer is an end product but is made available using the control module ff201. examples of serial programming connect ions can correspond to those in the next section. .com .com .com .com 4 .com u datasheet
561 chapter 19 flash serial programming connection 19.2 connection example in single-chip mode (user power supply) when 1 is input to the mode pin md2 of th e user system placed in single-chip mode and 0 to the mode pin md0 from the taux and tmode pins of the af220/af210/af120/ af110, the system enters the flash memo ry serial programming mode. a connection example using the user po wer supply is given below. connection example in single-ch ip mode (user power supply used) figure 19.2-1 example of serial programming connection for mb90f387/s (user power supply used) taux3 tmode taux ttxd trxd tck tvcc gnd md2 md0 x0 md1 x1 p30 p31 c sin1 sot1 sck1 vcc vss connector dx10-28s mb90f387/s af220/af210/af120/af110 flash microcontroller programmer pins 3, 4, 9, 11, 16, 17, 18, 20, 24, 25 and 26 are open dx10-28s: right-angle type connector (made by hirose electric co., ltd.) pin assignment user system 10 k ? 10 k ? 10 k ? 1mhz to 16mhz 10 k ? 10 k ? 10 k ? 10 k ? 0.1 f user user user power supply (12) (19) (23) (10) (5) (13) (27) (6) (2) (7, 8, 14, 15, 21, 22, 1, 28) rst 14 pin dx10-28s 1 pin 15 pin 28 pin /tres /tics .com .com .com .com 4 .com u datasheet
562 chapter 19 flash serial programming connection figure 19.2-2 control circuit notes: even if the sin1, sot1, and sck1 pins are us ed for the user system, the controller shown in the figure below is required in the same as p30. the /t ics signal of the flash microcontroller programmer can be used to disconnect the user circuit during serial programming. connect the af220/af210/af120/af110 while the user power is off. af220/af210/af120/af110 programming control pin mb90f387/s programming control pin af220/af210/af120/af110 /tics pin user 10 k ? .com .com .com .com 4 .com u datasheet
563 chapter 19 flash serial programming connection 19.3 connection example in single-chip mode (writer power supply) when 1 is input to the mode pin md2 of th e user system placed in single-chip mode and 0 to the mode pin md0 from the taux and tmode pins of the af220/af210/af210/ af120/af110, the system enters the flash memory serial programming mode. a connection example using the writer power supply is given below. connection example in single-chip mode (power supplied from flash microcontroller programmer) figure 19.3-1 example of serial pr ogramming connection for mb90f387/s (power supplied from flash microcontroller programmer) taux3 tmode taux ttxd trxd tck vcc tvcc tvpp1 gnd md2 md0 x0 md1 x1 p30 p31 c sin1 sot1 sck1 vcc vss connector dx10-28s mb90f387/s pins 4, 9, 11, 17, 18, 20, 24, 25 and 26 are open dx10-28s: right-angle type connector (made by hirose electric co., ltd.) pin assignment usersystem 10 k ? 10 k ? 10 k ? 1mhz to 16mhz 10 k ? 10 k ? 10 k ? 10 k ? 0.1 f user user user power supply (12) (19) (23) (10) (5) (13) (27) (6) (2) (3) (16) (7, 8, 14, 15, 21, 22, 1, 28) rst 14 pin dx10-28s 1 pin 15 pin 28 pin /tres /tics af220/af210/af120/af110 flash microcontroller programmer .com .com .com .com 4 .com u datasheet
564 chapter 19 flash serial programming connection figure 19.3-2 control circuit notes: even if the sin1, sot1, and sck1 pins are us ed for the user system, the controller shown in the figure below is required in the same as p30 (f igure 19.3-2). the /tic s signal of the flash microcontroller programmer can be used to disconnect the user circuit during serial programming connect the af220/af210/af120/af110 while the user power is off. when supplying programming power from af220/af210/af120/af110, do not short-circuit the programming power and user power. af220/af210/af120/af110 programming control pin mb90f387/s programming control pin af220/af210/af120/af110 /tics pin user 10 k ? .com .com .com .com 4 .com u datasheet
565 chapter 19 flash serial programming connection 19.4 example of minimum connect ion to flash microcontroller programmer (user power supply) when each pin is set as shown below at programming to flash memory, there is no need for connections between md2, md 0, p30 and the flash microcontroller programmer. example of minimum connection to flash microcontroller programmer (user power supply used) figure 19.4-1 example of minimum connecti on to the flash microcontroller programmer (user power supply used) ttxd trxd tck tvcc gnd md2 md0 md1 x0 x1 p30 p31 c sin1 sot1 sck1 vcc vss connector dx10-28s mb90f387/s pins 3, 4, 9, 10, 11, 12, 16, 17, 18, 19, 20, 23, 24, 25 and 26 are open dx10-28s: right-angle type connector (made by hirose electric co., ltd.) pin assignment user system 10 k ? 10 k ? 10 k ? 10 k ? 1mhz to 16mhz 0.1 f user power supply (5) (13) (27) (6) (2) (7, 8, 14, 15, 21, 22, 1,28) rst 14 pin dx10-28s 1 pin 15 pin 28 pin 10 k ? 10 k ? 10 k ? user circuit 10 k ? 10 k ? user circuit 1 for serial programming 1 for serial programming 0 for serial programming 0 for serial programming /tres 1 for serial programming af220/af210/af120/af110 flash microcontroller programmer .com .com .com .com 4 .com u datasheet
566 chapter 19 flash serial programming connection figure 19.4-2 control circuit notes: even if the sin1, sot1, and sck1 pins are us ed for the user system, the controller shown in the figure below is required. the /tics signal of th e flash microcontroller prog rammer can be used to disconnect the user circuit during serial programming. connect the af220/af210/af120/af110 while the user power is off. af220/af210/af120/af110 programming control pin mb90f387/s programming control pin af220/af210/af120/af110 /tics pin user 10 k ? .com .com .com .com 4 .com u datasheet
567 chapter 19 flash serial programming connection 19.5 example of minimum connect ion to flash microcontroller programmer (writer power supply) when each pin is set as shown below at programming to flash memory, there is no need for connections between md2, md 0, p30 and the flash microcontroller programmer. example of minimum connection to flash microcontroller programmer (power supplied from flash microcontroller programmer) figure 19.5-1 example of minimum connecti on to the flash microcontroller programmer (power supplied from flash microcontroller programmer) ttxd trxd tck tvcc gnd md2 md0 md1 x0 x1 p30 p31 c sin1 sot1 sck1 vcc vss connector dx10-28s mb90f387/s pins 4, 9, 10, 11, 12, 17, 18, 19, 20, 23, 24, 25 and 26 are open dx10-28s: right-angle type connector (made by hirose electric co., ltd.) pin assignment user system 10 k ? 10 k ? 10 k ? 10 k ? 1mhz to 16mhz 0.1 f (5) (13) (27) (7, 8, 14, 15, 21,22, 1, 28) rst 14 pin dx10-28s 1 pin 15 pin 28 pin 10 k ? 10 k ? 10 k ? user circuit 10 k ? 10 k ? user circuit 1 for serial programming 1 for serial programming 0 for serial programming 0 for serial programming (6) (2) (3) (16) /tres 1 for serial programming af220/af210/af120/af110 flash microcontroller programmer .com .com .com .com 4 .com u datasheet
568 chapter 19 flash serial programming connection figure 19.5-2 control circuit notes: even if the sin1, sot1, and sck1 pins are us ed for the user system, the controller shown in the figure below is required. the /tics signal of th e flash microcontroller prog rammer can be used to disconnect the user circuit during serial programming. connect the af220/af210/af120/af110 while the user power is off. when supplying programming power from af220/af210/af120/af110, do not short-circuit the programming power and user power. af220/af210/af120/af110 programming control pin mb90f387/s programming control pin af220/af210/af120/af110 /tics pin user 10 k ? .com .com .com .com 4 .com u datasheet
569 appendix the appendices provide the i/ o map and outline of instructions. appendix a instructions appendix b register index appendix c pin function index appendix d interrupt vector index .com .com .com .com 4 .com u datasheet
570 appendix appendix a instructions appendix a describes the i nstructions used by the f 2 mc-16lx. a.1 instruction types a.2 addressing a.3 direct addressing a.4 indirect addressing a.5 execution cycle count a.6 effective address field a.7 how to read the instruction list a.8 f 2 mc-16lx instruction list a.9 instruction map .com .com .com .com 4 .com u datasheet
571 appendix a instructions a.1 instruction types the f 2 mc-16lx supports 351 types of inst ructions. addr essing is enab led by using an effective address field of each instruction or using the inst ruction code itself. instruction types the f 2 mc-16lx supports the following 351 types of instructions: 41 transfer instructions (byte) 38 transfer instructions (word or long word) 42 addition/subtraction instructions (byte, word, or long word) 12 increment/decrement instructio ns (byte, word, or long word) 11 comparison instructions (byte, word, or long word) 11 unsigned multiplication/division instructions (word or long word) 11 signed multiplication/division instructions (word or long word) 39 logic instructions (byte or word) 6 logic instructions (long word) 6 sign inversion instructions (byte or word) 1 normalization instruction (long word) 18 shift instructions (byte, word, or long word) 50 branch instructions 6 accumulator operation inst ructions (byte or word) 28 other control instructions (byte, word, or long word) 21 bit operation instructions 10 string instructions .com .com .com .com 4 .com u datasheet
572 appendix a.2 addressing with the f 2 mc-16lx, the address format is determi ned by the instruction effective address field or the instruction code itself (implied). when the address format is determined by the instructi on code itself, specify an ad dress in accordance with the instruction code used. some instructions permit the user to select several types of addressing. addressing the f 2 mc-16lx supports the following 23 types of addressing: immediate (#imm) register direct direct branch address (addr16) physical direct branch address (addr24) i/o direct (io) abbreviated dir ect address (dir) direct address (addr16) i/o direct bit address (io:bp) abbreviated direct bit address (dir:bp) direct bit address (addr16:bp) vector address (#vct) register indirect (@rwj j = 0 to 3) register indirect with post increment (@rwj+ j = 0 to 3) register indirect with displacem ent (@rwi + disp8 i = 0 to 7, @rwj+ disp16 j = 0 to 3) long register indirect with disp lacement (@rli + disp8 i = 0 to 3) program counter indi rect with displacem ent (@pc + disp16) register indirect with base index (@rw0 + rw7, @rw1 + rw7) program counter relative branch address (rel) register list (rlst) accumulator indirect (@a) accumulator indirect branch address (@a) indirectly-specified branch address (@ear) indirectly-specified branch address (@eam) .com .com .com .com 4 .com u datasheet
573 appendix a instructions effective address field table a.2-1 lists the address formats sp ecified by the effec tive address field. table a.2-1 effective address field code representation address format default bank 00 r0 rw0 rl0 register direct: individual parts correspond to the byte, word, and long word types in order from the left. none 01 r1 rw1 (rl0) 02 r2 rw2 rl1 03 r3 rw3 (rl1) 04 r4 rw4 rl2 05 r5 rw5 (rl2) 06 r6 rw6 rl3 07 r7 rw7 (rl3) 08 @rw0 register indirect dtb 09 @rw1 dtb 0a @rw2 adb 0b @rw3 spb 0c @rw0+ register indirect with post increment dtb 0d @rw1+ dtb 0e @rw2+ adb 0f @rw3+ spb 10 @rw0+disp8 register indirect with 8-bit displacement dtb 11 @rw1+disp8 dtb 12 @rw2+disp8 adb 13 @rw3+disp8 spb 14 @rw4+disp8 register indirect with 8-bit displacement dtb 15 @rw5+disp8 dtb 16 @rw6+disp8 adb 17 @rw7+disp8 spb 18 @rw0+disp16 register indirect with 16-bit displacement dtb 19 @rw1+disp16 dtb 1a @rw2+disp16 adb 1b @rw3+disp16 spb 1c @rw0+rw7 register indirect with index register indirect with index pc indirect with 16-bit displacement direct address dtb 1d @rw1+rw7 dtb 1e @pc+disp16 pcb 1f addr16 dtb .com .com .com .com 4 .com u datasheet
574 appendix a.3 direct addressing an operand value, register, or address is specified explicitly in direct addressing mode. direct addressing immediate addressing (#imm) specify an operand value explicitly (#imm4/ #imm8/ #imm16/ #imm32). figure a.3-1 example of immediate addressing (#imm) register direct addressing specify a register explicitly as an operand. table a.3-1 lists the registers that can be specified. figure a.3- 2 shows an example of regi ster direct addressing. movw a, #01212h (this instruction stores the operand value in a.) before execution a 2 2 3 3 4 4 5 5 after execution a 4 4 5 5 1 2 1 2 (some instructions transfer al to ah.) table a.3-1 direct addressing registers general-purpose register byte r0, r1, r2, r3, r4, r5, r6, r7 word rw0, rw1, rw2, rw3, rw4, r5w, rw6, rw7 long word rl0, rl1, rl2, rl3 special-purpose register accumulator a, al pointer sp * bank pcb, dtb, usb, ssb, adb page dpr control ps, ccr, rp, ilm *: one of the user stack pointer (usp) and system stack pointer (ssp) is selected and used depending on the value of the s flag bit in the condition code re gister (ccr). for branch instructions, the program counter (pc) is not specified in an inst ruction operand but is specified implicitly. .com .com .com .com 4 .com u datasheet
575 appendix a instructions figure a.3-2 example of register direct addressing direct branch addressing (addr16) specify an offset exp licitly for the branch destination address. the size of the offset is 16 bits, which indicates the branch destination in the logical addr ess space. direct branch addressing is used for an unconditional branch, subroutine call, or software interr upt instruction. bits 23 to 16 of the address are specified by the program bank register (pcb). figure a.3-3 example of direct branch addressing (addr16) mov r0, a before execution a 0 7 1 6 2 5 3 4 after execution a 0 7 1 6 2 5 6 4 (this instruction transfers the eight low-order bits of a to the general-purpose register r0.) ? ? r0 memory space 3 4 r0 memory space jmp 3b20h before execution pc 3 c 2 0 after execution (this instruction causes an unconditional branch by direct branch addressing in a bank.) pcb 4 f pc 3 b 2 0 pcb 4 f 4f3c22h 3 b 4f3c21h 2 0 4f3c20h 6 2 jmp 3b20h memory space next instruction 4f3b20h .com .com .com .com 4 .com u datasheet
576 appendix physical direct branch addressing (addr24) specify an offset expl icitly for the branch destination address. the size of the offset is 24 bits. physical direct branch addressing is used for unconditional bran ch, subroutine call, or software interrupt instruction. figure a.3-4 example of direct branch addressing (addr24) i/o direct addressing (io) specify an 8-bit offset ex plicitly for the memory a ddress in an operand. the i/o address space in the physical address space from 000000 h to 0000ff h is accessed regardless of the data bank register (dtb) and direct page register (dpr). a bank select prefix for bank addressing is invalid if specified before an instruction using i/o direct addressing. figure a.3-5 example of i/o direct addressing (io) jmpp 333b20h before execution pc 3 c 2 0 after execution pcb 4 f pc 3 b 2 0 pcb 3 3 4f3c23h 3 3 4f3c22h 3 b 4f3c21h 2 0 4f3c20h 6 3 jmpp 333b20h memory space next instruction 333b20h (this instruction causes an unconditional branch by direct branch 24-bit addressing.) movw a, i:0c0h (this instruction reads data by i/o direct addressing and stores it in a.) before execution a 0 7 1 6 2 5 3 4 after execution a 2 5 3 4 f f e e f f memory space e e 0000c1h 0000c0h .com .com .com .com 4 .com u datasheet
577 appendix a instructions abbreviated direct addressing (dir) specify the eight low-order bits of a memory address explicitly in an operand. address bits 8 to 15 are specified by the direct page register (dpr). addres s bits 16 to 23 are specified by the data bank register (dtb). figure a.3-6 example of abbreviated direct addressing (dir) direct addressing (addr16) specify the 16 low-order bits of a memory address expl icitly in an operand. address bits 16 to 23 are specified by the data bank register (dtb). a prefix instruction for access space addressing is invalid for this mode of addressing. figure a.3-7 example of direct addressing (addr16) 4 4 5 5 1 2 1 2 6 6 6 6 ? ? 1 2 4 4 5 5 1 2 1 2 7 7 dtb 7 7 dtb 776620h 776620h before execution after execution movw s;20h, a memory space memory space a a (this instruction writes the contents of the eight low-order bits of a in abbreviated direct addressing mode.) 3 c 2 0 pc f f f e 4 f pcb 3 b 2 0 pc 4 f pcb 4f3c22h 4f3c21h 6 0 4f3c20h bra 3b20h 4f3b20h bra 3b20h before execution after execution memory space (this instruction causes an unconditional relative branch.) .com .com .com .com 4 .com u datasheet
578 appendix i/o direct bit addressing (io:bp) specify bits in physical addresses 000000 h to 0000ff h explicitly. bit positions are indicated by ":bp", where the larger number indicates th e most significant bit (msb) and th e lower number indicates the least significant bit (lsb). figure a.3-8 example of i/o direct bit addressing (io:bp) abbreviated direct bit addressing (dir:bp) specify the eight low-order bits of a memory address explicitly in an operand. address bits 8 to 15 are specified by the direct page register (dpr). addres s bits 16 to 23 are specified by the data bank register (dtb). bit positions are indicated by ":bp", where the larger number indicat es the most significant bit (msb) and the lower number indicates the least significant bit (lsb). figure a.3-9 example of abbrevia ted direct bit addressing (dir:bp) direct bit addressing (addr16:bp) specify arbitrary bits in 64 kilobytes explicitly. address bits 16 to 23 are specified by the data bank register (dtb). bit positions are indicated by ":bp", where the larger number indicates the most significant bit (msb) and the lower number indicat es the least significant bit (lsb). figure a.3-10 example of direct bit addressing (addr16:bp) 0 0 0 1 0000c1h 0000c1h before execution after execution setb i:0c1h: memory space (this instruction sets bits by i/o direct bit addressing.) setb s:10h:0 5 5 dtb 5 5 0 0 0 1 dtb 6 6 dpr 6 6 dpr 556610h 556610h before execution after execution memory space memory space (this instruction sets bits by abbreviated direct bit addressing.) setb 2222h:0 5 5 dtb 5 5 0 0 0 1 dtb 552222h 552222h before execution after execution memory space memory space (this instruction sets bits by direct bit addressing.) .com .com .com .com 4 .com u datasheet
579 appendix a instructions vector addressing (#vct) specify vector data in an operand to indicate the branch destination addr ess. there are two sizes for vector numbers: 4 bits and 8 bits. vector addressing is used for a subroutine call or software interrupt instruction. figure a.3-11 example of vector addressing (#vct) callv #15 0 0 0 0 pc f f pcb f f d 0 d 0 0 0 pc pcb ffffe1h 0 0 ffffe0h e f ffc000h callv #15 before execution after execution memory space (this instruction causes a branch to the address indicated by the interrupt vector specified in an operand.) table a.3-2 callv vector list instruction vector address l vector address h callv #0 xxfffe h xxffff h callv #1 xxfffc h xxfffd h callv #2 xxfffa h xxfffb h callv #3 xxfff8 h xxfff9 h callv #4 xxfff6 h xxfff7 h callv #5 xxfff4 h xxfff5 h callv #6 xxfff2 h xxfff3 h callv #7 xxfff0 h xxfff1 h callv #8 xxffee h xxffef h callv #9 xxffec h xxffed h callv #10 xxffea h xxffeb h callv #11 xxffe8 h xxffe9 h callv #12 xxffe6 h xxffe7 h callv #13 xxffe4 h xxffe5 h callv #14 xxffe2 h xxffe3 h callv #15 xxffe0 h xxffe1 h note: a pcb register value is set in xx. note: when the program bank register (pcb) is ff h , the vector area overlaps the vector area of int #vct8 (#0 to #7). use vector addressi ng carefully (see table a.3-2). .com .com .com .com 4 .com u datasheet
580 appendix a.4 indirect addressing in indirect addressing mode, an address is specified indirectly by the address data of an operand. indirect addressing register indirect addressing (@rwj j = 0 to 3) memory is accessed using the contents of general-purpos e register rwj as an address. address bits 16 to 23 are indicated by the data bank register (dtb) wh en rw0 or rw1 is used, sy stem stack bank register (ssb) or user stack bank register (usb) when rw3 is used, or additional data bank register (adb) when rw2 is used. figure a.4-1 example of register indirect addressing (@rwj j = 0 to 3) register indirect addressing with post increment (@rwj+ j = 0 to 3) memory is accessed using the contents of general-purpose register rwj as an address. after operand operation, rwj is incremented by the operand size (1 for a byte, 2 for a word, or 4 for a long word). address bits 16 to 23 are indicated by the data ba nk register (dtb) when rw0 or rw1 is used, system stack bank register (ssb) or user stack bank regist er (usb) when rw3 is used, or additional data bank register (adb) when rw2 is used. if the post increment results in the address of the re gister that specifies the increment, the incremented value is referenced after that. in th is case, if the next instruction is a write instruction, priority is given to writing by an instruction and, therefore, the register that would be incremented becomes write data. movw a, @rw1 0 7 1 6 a d 3 0 f 2 5 3 4 rw1 f f e e 2 5 3 4 a d 3 0 f f f e e rw1 7 8 dtb 7 8 dtb 78d310h 78d30fh before execution after execution memory space (this instruction reads data by register indirect addressing and stores it in a.) .com .com .com .com 4 .com u datasheet
581 appendix a instructions figure a.4-2 example of register indirect addressing with post increment (@rwj + j = 0 to 3) register indirect addressing with offset (@rwi + disp8 i = 0 to 7, @rwj + disp16 j = 0 to 3) memory is accessed using the address obtained by adding an offset to the cont ents of general-purpose register rwj. two types of offset, byte and word of fsets, are used. they are added as signed numeric values. address bits 16 to 23 are indicated by the da ta bank register (dtb) when rw0, rw1, rw4, or rw5 is used, system stack bank regi ster (ssb) or user stack bank re gister (usb) when rw3 or rw7 is used, or additional data bank register (adb) when rw2 or rw6 is used. figure a.4-3 example of register indirect addressing with offset (@rwi + disp8 i = 0 to 7, @rwj + disp16 j = 0 to 3) long register indirect addressing with offset (@rli + disp8 i = 0 to 3) memory is accessed using the address th at is the 24 low-order bits obta ined by adding an offset to the contents of general-purpose register rl i. the offset is 8-bits long and is added as a signed numeric value. figure a.4-4 example of long register indirect addressing with offset (@rli + disp8 i = 0 to 3) movw a, @rw1+ 0 7 1 6 a d 3 0 f 2 5 3 4 rw1 f f e e 2 5 3 4 a d 3 1 1 f f e e rw1 7 8 dtb 7 8 dtb 78d310h 78d30fh before execution after execution memory space (this instruction reads data by register indirect addressing with post increment and stores it in a.) movw 0 7 1 6 a a, @rw1+10h d 3 0 f 2 5 3 4 rw1 f f e e 2 5 3 4 a d 3 0 f f f e e rw1 7 8 dtb 7 8 dtb 78d320h 78d31fh (+10h) before execution after execution memory space (this instruction reads data by register indirect addressing with an offset and stores it in a.) movw a, @rl2+25h 0 7 1 6 a 2 5 3 4 f 3 8 2 4 b 0 2 rl2 f f e e 2 5 3 4 a f f e e f 3 8 2 4 b 0 2 rl2 824b28h 824b27h (+25h) before execution after execution memory space (this instruction reads data by long register indirect addressing with an offset and stores it in a.) .com .com .com .com 4 .com u datasheet
582 appendix program counter indirect addressing with offset (@pc + disp16) memory is accessed using the address in dicated by (instruction address + 4 + disp16). the offset is one word long. address bits 16 to 23 are specified by the program bank regi ster (pcb). note that the operand address of each of the follo wing instructions is not deemed to be (next instruction address + disp16): dbnz eam, rel dwbnz eam, rel cbne eam, #imm8, rel cwbne eam, #imm16, rel mov eam, #imm8 movw eam, #imm16 figure a.4-5 example of program counter indi rect addressing with offset (@pc + disp16) register indirect addressing with base index (@rw0 + rw7, @rw1 + rw7) memory is accessed using the address determined by adding rw0 or rw1 to the contents of general- purpose register rw7. address bits 16 to 23 are indicated by the data bank register (dtb). figure a.4-6 example of register indirect addr essing with base index (@rw0 + rw7, @rw1 + rw7) movw a, @pc+20h 0 7 1 6 a 2 5 3 4 c 5 pcb c 5 f f e e 0 0 2 0 movw a, @pc+20h 2 5 3 4 a f f e e pcb c5457bh c5457ah c54559h c54558h 9 e 7 3 c54557h c54556h c5455ah +20h +4 4 5 5 6 pc 4 5 5 a pc before execution after execution memory space (this instruction reads data by program counter indirect addressing with a offset and stores it in a.) movw a, @rw1+rw7 0 7 1 6 a d 3 0 f 2 5 3 4 rw1 f f e e 2 5 3 4 a d 3 0 f f f e e rw1 0 1 0 1 rw7 7 8 dtb 0 1 0 1 rw7 7 8 dtb 78d411h 78d410h + before execution after execution memory space (this instruction reads data by register indirect addressing with a base index and stores it in a.) .com .com .com .com 4 .com u datasheet
583 appendix a instructions program counter relative branch addressing (rel) the address of the branch destination is a value de termined by adding an 8-bit offset to the program counter (pc) value. if the result of addition exceeds 16 b its, bank register increm enting or decrementing is not performed and the excess part is ignored, and ther efore the address is contained within a 64-kilobyte bank. this addressing is used for both conditional an d unconditional branch instructions. address bits 16 to 23 are indicated by the pr ogram bank register (pcb). figure a.4-7 example of program count er relative branch addressing (rel) register list (rlst) specify a register to be pushed onto or popped from a stack. figure a.4-8 configuration of the register list bra 3b20h 3 c 2 0 pc f f f e 4 f pcb 3 b 2 0 pc 4 f pcb 4f3c22h 4f3c21h 6 0 4f3c20h bra 3b20h 4f3b20h before execution after execution memory space (this instruction causes an unconditional relative branch.) next instruction a register is selected when the corresponding bit is 1 and deselected when the bit is 0. msb lsb rw7 rw6 rw5 rw4 rw3 rw2 rw1 rw0 .com .com .com .com 4 .com u datasheet
584 appendix figure a.4-9 example of register list (rlist) accumulator indirect addressing (@a) memory is accessed using the address indicated by the contents of the low-order bytes (16 bits) of the accumulator (al). address bits 16 to 23 are specified by a mnemonic in the data bank register (dtb). figure a.4-10 example of accu mulator indirect addressing (@a) popw rw0, rw4 3 4 f a sp rw0 rw1 rw2 rw3 rw4 rw5 rw6 rw7 0 4 0 3 34fdh 34fch 34feh 0 2 0 1 34fbh 34fah sp 3 4 f e sp 0 1 0 2 rw0 rw1 rw2 rw3 rw4 rw5 rw6 rw7 0 3 0 4 0 4 0 3 34fdh 34fch 34feh 0 2 0 1 34fbh 34fah sp before execution after execution memory space memory space (this instruction transfers memory data indicated by the sp to multiple word registers indicated by the register list.) movw a, @a 0 7 1 6 a 2 5 3 4 dtb f f e e 0 7 1 6 a f f e e dtb b b b b bb2535h bb2534h before execution after execution memory space (this instruction reads data by accumulator indirect addressing and stores it in a.) .com .com .com .com 4 .com u datasheet
585 appendix a instructions accumulator indirect branch addressing (@a) the address of the branch destina tion is the content (16 bits) of the low-order bytes (al) of the accumulator. it indicates the bran ch destination in the bank addre ss space. address bits 16 to 23 are specified by the program bank register (pcb). for the jump context (jct x) instruction, however, address bits 16 to 23 are specified by th e data bank register (dtb). this addressing is used for unconditional branch instructions. figure a.4-11 example of accumulator indirect branch addressing (@a) indirect specification branch addressing (@ear) the address of the branch dest ination is the word data at the address indicated by ear. figure a.4-12 example of indirect specification branch addressing (@ear) jmp @a 6 6 7 7 a 3 b 2 0 6 1 3 c 2 0 pc 4 f pcb 6 6 7 7 a 3 b 2 0 3 b 2 0 pc 4 f pcb 4f3c20h jmp @a 4f3b20h before execution after execution memory space (this instruction causes an unconditional branch by accumulator indirect branch addressing.) next instruction jmp @@rw0 0 8 3 c 2 0 pc 7 f 4 8 pw0 4 f pcb 2 1 dtb 3 b 2 0 pc 7 f 4 8 pw0 4 f pcb 2 1 dtb 4f3c21h 7 3 4f3c20h 3 b 217f49h 2 0 217f48h jmp @@rw0 4f3b20h before execution after execution memory space (this instruction causes an unconditional branch by register indirect addressing.) next instruction .com .com .com .com 4 .com u datasheet
586 appendix indirect specification branch addressing (@eam) the address of the branch dest ination is the word data at the address indicated by eam. figure a.4-13 example of indirect sp ecification branch addressing (@eam) jmp @rw0 0 0 3 c 2 0 pc 3 b 2 0 pw0 4 f pcb 3 b 2 0 pc 3 b 2 0 pw0 4 f pcb 4f3c21h 7 3 4f3c20h jmp @rw0 4f3b20h before execution after execution memory space (this instruction causes an unconditional branch by register indirect addressing.) next instruction .com .com .com .com 4 .com u datasheet
587 appendix a instructions a.5 execution cycle count the number of cycles requir ed for instruction execution (execution cycle count) is obtained by adding the number of cycles required for each instruction, "correction value" determined by the condi tion, and the number of cycles for instruction fetch. execution cycle count the number of cycles required for in struction execution (ex ecution cycle count) is obtained by adding the number of cycles required for each instruction, "cor rection value" determined by the condition, and the number of cycles for instruction fetch. in the mode of fetching an instruction from memory such as internal rom connected to a 16-bit bus, the program fetches the instruction being execu ted in word increments. therefore, intervening in data acce ss increases the execution cycle count. similarly, in the mode of fetching an instruction fr om memory connected to an 8-bit external bus, the program fetches every byte of an instruction being executed. therefore, in tervening in data access increases the execution cy cle count. in cpu intermittent op eration mode, access to a general-purpose register, internal rom, internal ram, internal i/o, or external data bus causes the clock to the cpu to halt for the cycle count specified by the cg0 and cg1 bits of the low power consumption mode control register. therefore, for the cycle count required fo r instruction execution in cpu intermittent operation mode, add the "access count x cycle count for the halt" as a correction value to the normal execution count. .com .com .com .com 4 .com u datasheet
588 appendix calculating the ex ecution cycle count table a.5-1 lists execution cycle counts and table a.5-2 and table a.5-3 summarize correction value data. table a.5-1 execution cycle counts in each addressing mode code operand (a) * register access count in each addressing mode execution cycle count in each addressing mode 00 to 07 ri rwi rli see the instruction list. s ee the instruction list. 08 to 0b @rwj 2 1 0c to 0f @rwj+ 4 2 10 to 17 @rwi+disp8 2 1 18 to 1b @rwi+disp16 2 1 1c 1d 1e 1f @rw0+rw7 @rw1+rw7 @pc+disp16 addr16 4 4 2 1 2 2 0 0 * : (a) is used for (cycle count) and b (correction value) in "a.8 f 2 mc-16lx instruction list". .com .com .com .com 4 .com u datasheet
589 appendix a instructions table a.5-2 cycle count correction values for counting execution cycles operand (b) byte (*) (c) word (*) (d) long (*) cycle count access count cycle count access count cycle count access count internal register +0 1 +0 1 +0 2 internal memory even address +0 1 +01+02 internal memory odd address +0 1 +22+44 external data bus 16-bit even address +1 1 +11+22 external data bus 16-bit odd address +1 1 +42+84 external data bus 8-bits +1 1 +42+84 * : (b), (c), and (d) are used for (cycle count) and b (correction value) in "a.8 f 2 mc-16lx instruction list". note: when an external data bus is used, the cycle count s during which an instruction is made to wait by ready input or automatic ready must also be added. table a.5-3 cycle count correction values for counting instruction fetch cycles instruction byte boundary word boundary internal memory - +2 external data bus 16-bits - +3 external data bus 8-bits +3 - notes: when an external data bus is used, the cycle co unts during which an instruction is made to wait by ready input or automatic read y must also be added. actually, instruction execution is not delayed by ever y instruction fetch. ther efore, use the correction values to calculate the worst case. .com .com .com .com 4 .com u datasheet
590 appendix a.6 effective address field table a.6-1 shows the effective address field. effective address field table a.6-1 effective address field code representation address format byte count of extended address part * 00 r0 rw0 rl0 register direct: individual parts correspond to the byte, word, and long word types in order from the left. - 01 r1 rw1 (rl0) 02 r2 rw2 rl1 03 r3 rw3 (rl1) 04 r4 rw4 rl2 05 r5 rw5 (rl2) 06 r6 rw6 rl3 07 r7 rw7 (rl3) 08 @rw0 register indirect 0 09 @rw1 0a @rw2 0b @rw3 0c @rw0+ register indirect with post increment 0 0d @rw1+ 0e @rw2+ 0f @rw3+ 10 @rw0+disp8 register indirect with 8-bit displacement 1 11 @rw1+disp8 12 @rw2+disp8 13 @rw3+disp8 14 @rw4+disp8 15 @rw5+disp8 16 @rw6+disp8 17 @rw7+disp8 18 @rw0+disp16 register indirect with 16-bit displacement 2 19 @rw1+disp16 1a @rw2+disp16 1b @rw3+disp16 1c @rw0+rw7 register indirect with index 0 1d @rw1+rw7 register indirect with index 0 1e @pc+disp16 pc indirect with 16-bit displacement 2 1f addr16 direct address 2 *: each byte count of the exte nded address part applies to + in the # (byte count) column in "a.8 f 2 mc-16lx instruction list" . .com .com .com .com 4 .com u datasheet
591 appendix a instructions a.7 how to read the instruction list table a.7-1 describes t he items used in the f 2 mc-16lx instruction li st, and table a.7-2 describes the symbols used in the same list. description of instructi on presentation items and symbols table a.7-1 description of items in the instruction list (1/2) item description mnemonic uppercase, symbol: represented as is in the assembler. lowercase: rewritten in the assembler. number of following lowercase: indicates bit length in the instruction. # indicates the number of bytes. indicates the number of cycles. see table a.2-1 for the alph abetical letters in items. rg indicates the number of times a regist er access is performed during instruction execution. the number is used to calculate the correction value for cpu intermittent operation. b indicates the correction value used to calcu late the actual number of cycles during instruction execution. the actual number of cycles during inst ruction execution can be determined by adding the value in the ~ column to this value. operation indicates the instruction operation. lh indicates the special operation for bits 15 to 08 of the accumulator. z: transfers 0. x: transfers after sign extension. -: no transfer ah indicates the special operation for the 16 high-order bits of the accumulator. *: transfers from al to ah. -: no transfer z: transfers 00 to ah. x: transfers 00h or ffh to ah after al sign extension. .com .com .com .com 4 .com u datasheet
592 appendix i each indicates the state of each flag:i (interrupt enable), s (stack), t (sticky bit), n (negative), z (zero), v (overflow), c (carry). *: changes upon instruction execution. -: no change z: set upon instruction execution. x: reset upon instruction execution. s t n z v c rmw indicates whether the instruction is a read modify write instruction (reading data from memory by the i instruction and writing the result to memory). *: read modify write instruction -: not read modify write instruction note: cannot be used for an address that has different meanings between read and write operations. table a.7-2 explanation on symbols in the instruction list (1/2) symbol explanation a the bit length used varies depending on the 32-bit accumulator instruction. byte: low-order 8 bits of byte al word: 16 bits of word al long word: 32 bits of al and ah ah 16 high-order bits of a al 16 low-order bits of a sp stack pointer (usp or ssp) pc program counter pcb program bank register dtb data bank register adb additional data bank register ssb system stack bank register usb user stack bank register spb current stack bank re gister (ssb or usb) dpr direct page register brg1 dtb, adb, ssb, usb, dpr, pcb, spb brg2 dtb, adb, ssb, usb, dpr, spb table a.7-1 description of items in the instruction list (2/2) item description .com .com .com .com 4 .com u datasheet
593 appendix a instructions ri r0, r1, r2, r3, r4, r5, r6, r7 rwi rw0, rw1, rw2, rw3, rw4, rw5, rw6, rw7 rwj rw0, rw1, rw2, rw3 rli rl0, rl1, rl2, rl3 dir abbreviated direct addressing addr16 direct addressing addr24 physical direct addressing ad24 0-15 bits 0 to 15 of addr24 ad24 16-23 bits 16 to 23 of addr24 io i/o area (000000 h to 0000ff h ) #imm4 4-bit immediate data #imm8 8-bit immediate data #imm16 16-bit immediate data #imm32 32-bit immediate data ext (imm8) 16-bit data obtained by sign extension of 8-bit immediate data disp8 8-bit displacement disp16 16-bit displacement bp bit offset vct4 vector number (0 to 15) vct8 vector number (0 to 255) ( ) b bit address rel pc relative branch ear effective addressing (code 00 to 07) eam effective addressing (code 08 to 1f) rlst register list table a.7-2 explanation on symbols in the instruction list (2/2) symbol explanation .com .com .com .com 4 .com u datasheet
594 appendix a.8 f 2 mc-16lx instruction list table a.8-1 to table a.9-19 li st the instructions used by the f 2 mc-16lx. f 2 mc-16lx instruction list table a.8-1 41 transfer instructions (byte) mnemonic # rg b operation l h a h istnzvc r m w mov a,dir 2 3 0 (b) byte (a) <-- (dir) z*--**---- mov a,addr16 3 4 0 (b) byte (a) <-- (addr16) z*--**---- mov a,ri 1 2 1 0 byte (a) <-- (ri) z*--**---- mov a,ear 2 2 1 0 byte (a) <-- (ear) z*--**---- mov a,eam 2+ 3 + (a) 0 (b) byte (a) <-- (eam) z*--**---- mov a,io 2 3 0 (b) byte (a) <-- (io) z*--**---- mov a,#imm8 2 2 0 0 byte (a) <-- imm8 z*--**---- mov a,@a 2 3 0 (b) byte (a) <-- ((a)) z---**---- mov a,@rli+disp8 3 10 2 (b) byte (a) <-- ((rli)+disp8) z*--**---- movn a,#imm4 1 1 0 0 byte (a) <-- imm4 z*--r*---- movx a,dir 2 3 0 (b) byte (a) <-- (dir) x * - - - * * - - - movx a,addr16 3 4 0 (b) byte (a) <-- (addr16) x * - - - * * - - - movx a,ri 2 2 1 0 byte (a) <-- (ri) x * - - - * * - - - movx a,ear 2 2 1 0 byte (a) <-- (ear) x*---**--- movx a,eam 2+ 3 + (a) 0 (b) byte (a) <-- (eam) x * - - - * * - - - movx a,io 2 3 0 (b) byte (a) <-- (io) x * - - - * * - - - movx a,#imm8 2 2 0 0 byte (a) <-- imm8 x * - - - * * - - - movx a,@a 2 3 0 (b) byte (a) <-- ((a)) x - - - - * * - - - movx a,@rwi+disp8 2 5 1 (b) byte (a) <-- ((rwi)+disp8) x * - - - * * - - - movx a,@rli+disp8 3 10 2 (b) byte (a) <-- ((rli)+disp8 x * - - - * * - - - mov dir,a 2 3 0 (b) byte (dir) <-- (a) - - - - - * * - - - mov addr16,a 3 4 0 (b) byte (addr16) <-- (a) - - - - - * * - - - mov ri,a 1 2 1 0 byte (ri) <-- (a) -----**--- mov ear,a 2 2 1 0 byte (ear) <-- (a) - - - - - * * - - - mov eam,a 2+ 3 + (a) 0 (b) byte (eam) <-- (a) - - - - - * * - - - mov io,a 2 3 0 (b) byte (io) <-- (a) - - - - - * * - - - mov @rli+disp8,a 3 10 2 (b) byte ((rli)+disp8) <-- (a) - - - - - * * - - - mov ri,ear 2 3 2 0 byte (ri) <-- (ear) -----**--- mov ri,eam 2+ 4 + (a) 1 (b) byte (ri) <-- (eam) - - - - - * * - - - mov ear,ri 2 4 2 0 byte (ear) <-- (ri) - - - - - * * - - - mov eam,ri 2+ 5 + (a) 1 (b) byte (eam) <-- (ri) - - - - - * * - - - mov ri,#imm8 2 2 1 0 byte (ri) <-- imm8 - - - - - * * - - - mov io,#imm8 3 5 0 (b) byte (io) <-- imm8 - - -------- mov dir,#imm8 3 5 0 (b) byte (dir) <-- imm8 ---------- mov ear,#imm8 3 2 1 0 byte (ear) <-- imm8 - - - - - * * - - - mov eam,#imm8 3+ 4 + (a) 0 (b) byte (eam) <-- imm8 ---------- mov @al,ah / mov @a,t 2 3 0 (b) byte ((a)) <-- (ah) - - - - - * * - - - xch a,ear 2 4 2 0 byte (a) <--> (ear) z--------- xch a,eam 2+ 5 + (a) 0 2 x (b) byte (a) <--> (eam) z--------- xch ri,ear 2 7 4 0 byte (ri) <--> (ear) ---------- xch ri,eam 2+ 9 + (a) 2 2 x (b) byte (ri) <--> (eam) ---------- note: see table a.5-1 and table a.5-2 for information on (a) to (d) in the table. .com .com .com .com 4 .com u datasheet
595 appendix a instructions table a.8-2 38 transfer instructions (byte) mnemonic # rg b operation l h a h istnzvcr m w movw a,dir 2 3 0 (c) word (a) <-- (dir) - * - - - * * - - - movw a,addr16 3 4 0 (c) word (a) <-- (addr16) - * - - - * * - - - movw a,sp 3 1 0 0 word (a) <-- (sp) - * - - - * * - - - movw a,rwi 1 2 1 0 word (a) <-- (rwi) -*---**--- movw a,ear 2 2 1 0 word (a) <-- (ear) -*---**--- movw a,eam 2+ 3 + (a) 0 (c) word (a) <-- (eam) - * - - - * * - - - movw a,io 2 3 0 (c) word (a) <-- (io) - * - - - * * - - - movw a,@a 2 3 0 (c) word (a) <-- ((a)) - - - - - * * - - - movw a,#imm16 3 2 2 0 word (a) <-- imm16 - * - - - * * - - - movw a,@rwi+disp8 2 5 1 (c) word (a) <-- ((rwi)+disp8) - * - - - * * - - - movw a,@rli+disp8 3 10 2 (c) word (a) <-- ((rli)+disp8) - * - - - * * - - - movw dir,a 2 3 0 (c) word (dir) <-- (a) - - - - - * * - - - movw addr16,a 3 4 0 (c) word (addr16) <-- (a) - - - - - * * - - - movw sp,a 1 1 0 0 word (sp) <-- (a) -----**--- movw rwi,a 1 2 1 0 word (rwi) <-- (a) - - - - - * * - - - movw ear,a 2 2 1 0 word (ear) <-- (a) - - - - - * * - - - movw eam,a 2+ 3 + (a) 0 (c) word (eam) <-- (a) - - - - - * * - - - movw io,a 2 3 0 (c) word (io) <-- (a) - - - - - * * - - - movw @rwi+disp8,a 2 5 1 (c) word ((rwi)+disp8) <-- (a) - - - - - * * - - - movw @rli+disp8,a 3 10 2 (c) word ((rli)+disp8) <-- (a) - - - - - * * - - - movw rwi,ear 2 3 2 0 word (rwi) <-- (ear) - - - - - * * - - - movw 2+ 4 + (a) 1 (c) word (rwi) <-- (eam) - - - - - * * - - - movw ear,rwi 2 4 2 0 word (ear) <-- (rwi) - - - - - * * - - - movw eam,rwi 2+ 5 + (a) 1 (c) word (eam) <-- (rwi) - - - - - * * - - - movw rwi,#imm16 3 2 1 0 word (rwi) <-- imm16 - - - - - * * - - - movw io,#imm16 4 5 0 (c) word (io) <-- imm16 - - -------- movw ear,#imm16 4 2 1 0 word (ear) <-- imm16 - - - - - * * - - - movw eam,#imm16 4+ 4 + (a) 0 (c) word (eam) <-- imm16 ---------- movw @al,ah / movw @a,t 2 3 0 (c) word ((a)) <-- (ah) - - - - - * * - - - xchw a,ear 2 4 2 0 word (a) <--> (ear) ---------- xchw a,eam 2+ 5 + (a) 0 2 x (c) word (a) <-- >(eam) ---------- xchw rwi, ear 2 7 4 0 word (rwi) <--> (ear) ---------- xchw rwi, eam 2+ 9 + (a) 2 2 x (c) word (rwi) <--> (eam) ---------- movl a,ear 2 4 2 0 long (a) <-- (ear) - - - - - * * - - - movl a,eam 2+ 5 + (a) 0 (d) long (a) <-- (eam) - - - - - * * - - - movl a,#imm32 5 3 0 0 long (a) <-- imm32 - - - - - * * - - - movl ear,a 2 4 2 0 long (ear1) <-- (a) - - - - - * * - - - movl eam,a 2+ 5 + (a) 0 (d) long(eam1) <-- (a) - - - - - * * - - - note: see table a.5-1 and table a.5-2 for information on (a) to (d) in the table. .com .com .com .com 4 .com u datasheet
596 appendix table a.8-3 42 addition/subtraction instructions (byte, word, long word) mnemonic # rg b operation l h a h istnzvc r m w add a,#imm8 2 2 0 0 byte (a) <-- (a) + imm8 z- - - -****- add a,dir 2 5 0 (b) byte (a) <-- (a) + (dir) z- - - -****- add a,ear 2 3 1 0 byte (a) <-- (a) + (ear) z- - - -****- add a,eam 2+ 4 + (a) 0 (b) byte (a) <-- (a) + (eam) z- - - -****- add ear,a 2 3 2 0 byte (ear) <-- (ear) + (a) - - - - -****- add eam,a 2+ 5 + (a) 0 2 x (b) byte (eam) <-- (eam) + (a) z- - - -***** addc a 1 2 0 0 byte (a) <-- (ah) + (al) + (c) z- - - -****- addc a,ear 2 3 1 0 byte (a) <-- (a) + (ear)+ (c) z- - - -****- addc a,eam 2+ 4 + (a) 0 (b) byte (a) <-- (a) + (eam)+ (c) z- - - -****- adddc a 1 3 0 0 byte (a) <-- (ah) + (al) + (c) (decimal) z- - - -****- sub a,#imm8 2 2 0 0 byte (a) <-- (a) - imm8 z- - - -****- sub a,dir 2 5 0 (b) byte (a) <-- (a) - (dir) z- - - -****- sub a,ear 2 3 1 0 byte (a) <-- (a) - (ear) z- - - -****- sub a,eam 2+ 4 + (a) 0 (b) byte (a) <-- (a) - (eam) z- - - -****- sub ear,a 2 3 2 0 byte (ear) <-- (ear) - (a) - - - - -****- sub eam,a 2+ 5 + (a) 0 2 x (b) byte (eam) <-- (eam) - (a) - - - - -***** subc a 1 2 0 0 byte (a) <-- (ah) - (al) - (c) z- - - -****- subc a,ear 2 3 1 0 byte (a) <-- (a) - (ear) - (c) z- - - -****- subc a,eam 2+ 4 + (a) 0 (b) byte (a) <-- (a) - (eam) - (c) z- - - -****- subdc a 1 3 0 0 byte (a) <-- (ah) - (al) - (c) (decimal) z- - - -****- addw a 1 2 0 0 word (a) <-- (ah) + (al) - - - - -****- addw a,ear 2 3 1 0 word (a) <-- (a) + (ear) - - - - -****- addw a,eam 2+ 4+(a) 0 (c) word (a) <-- (a) + (eam) - - - - -****- addw a,#imm16 3 2 0 0 word (a) <-- (a) + imm16 - - - - -****- addw ear,a 2 3 2 0 word (ear) <-- (ear) + (a) - - - - -****- addw eam,a 2+ 5+(a) 0 2 x (c) word (eam) <-- (eam) + (a) - - - - -***** addcw a,ear 2 3 1 0 word (a) <-- (a) + (ear) + (c) - - - - -****- addcw a,eam 2+ 4+(a) 0 (c) word (a) <-- (a) + (eam) + (c) - - - - -****- subw a 1 2 0 0 word (a) <-- (ah) - (al) - - - - -****- subw a,ear 2 3 1 0 word (a) <-- (a) - (ear) - - - - -****- subw a,eam 2+ 4+(a) 0 (c) word (a) <-- (a) - (eam) - - - - -****- subw a,#imm16 3 2 0 0 word (a) <-- (a) - imm16 - - - - -****- subw ear,a 2 3 2 0 word (ear) <-- (ear) - (a) - - - - -****- subw eam,a 2+ 5+(a) 0 2 x (c) word (eam) <-- (eam) - (a) - - - - -***** subcw a,ear 2 3 1 0 word (a) <-- (a) - (ear) - (c) - - - - -****- subcw a,eam 2+ 4+(a) 0 (c) word (a) <-- (a) - (eam) - (c) - - - - -****- addl a,ear 2 6 2 0 long (a) <-- (a) + (ear) - - - - - ****- addl a,eam 2+ 7+(a) 0 (d) long (a) <-- (a) + (eam) - - - - - ****- addl a,#imm32 5 4 0 0 long (a) <-- (a) + imm32 - - - - - ****- subl a,ear 2 6 2 0 long (a) <-- (a) - (ear) - - - - - ****- subl a,eam 2+ 7+(a) 0 (d) long (a) <-- (a) - (eam) - - - - - ****- subl a,#imm32 5 4 0 0 long (a) <-- (a) - imm32 - - - - - ****- note: see table a.5-1 and table a.5-2 for information on (a) to (d) in the table. .com .com .com .com 4 .com u datasheet
597 appendix a instructions table a.8-4 12 increment/decrement instructions (byte, word, long word) mnemonic # rg b operation l h a h istnzvc r m w inc ear 2 3 2 0 byte (ear) <-- (ear) + 1 - - - - - * * * - - inc eam 2+ 5+(a) 0 2 x (b) byte (eam) <-- (eam) + 1 - - - - - * * * - * dec ear 2 3 2 0 byte (ear) <-- (ear) - 1 -----***-- dec eam 2+ 5+(a) 0 2 x (b) byte (eam) <-- (eam) - 1 - - - - - * * * - * incw ear 2 3 2 0 word (ear) <-- (ear) + 1 - - - - - * * * - - incw eam 2+ 5+(a) 0 2 x (c) word (eam) <-- (eam) + 1 - - - - - * * * - * decw ear 2 3 2 0 word (ear) <-- (ear) - 1 - - - - - * * * - - decw eam 2+ 5+(a) 0 2 x (c) word (eam) <-- (eam) - 1 - - - - - * * * - * incl ear 2 7 4 0 long (ear) <-- (ear) + 1 - - - - - * * * - - incl eam 2+ 9+(a) 0 2 x (d) long (eam) <-- (eam) + 1 - - - - - * * * - * decl ear 2 7 4 0 long (ear) <-- (ear) - 1 - - - - - * * * - - decl eam 2+ 9+(a) 0 2 x (d) long (eam) <-- (eam) - 1 - - - - - * * * - * note: see table a.5-1 and table a.5-2 for information on (a) to (d) in the table. table a.8-5 11 compare instructions (byte, word, long word) mnemonic # rg b operation l h a h istnzvc r m w cmp a 1 1 0 0 byte (ah) - (al) - - - - -****- cmp a,ear 2 2 1 0 byte (a) - (ear) - - - - -****- cmp a,eam 2+ 3+(a) 0 (b) byte (a) - (eam) - - - - -****- cmp a,#imm8 2 2 0 0 byte (a) - imm8 - - - - -****- cmpw a 1 1 0 0 word (ah) - (al) - - - - -****- cmpw a,ear 2 2 1 0 word (a) - (ear) - - - - -****- cmpw a,eam 2+ 3+(a) 0 (c) word (a) - (eam) - - - - -****- cmpw a,#imm16 3 2 0 0 word (a) - imm16 - - - - -****- cmpl a,ear 2 6 2 0 long (a) - (ear) - - - - - ****- cmpl a,eam 2+ 7+(a) 0 (d) long (a) - (eam) - - - - - ****- cmpl a,#imm32 5 3 0 0 long (a) - imm32 - - - - - ****- note: see table a.5-1 and table a.5-2 for information on (a) to (d) in the table. .com .com .com .com 4 .com u datasheet
598 appendix table a.8-6 11 unsigned multiplication/division instructions (word, long word) mnemonic # rg b operation l h a h istnzvc r m w divu a 1 *1 0 0 word (ah) / byte (al) quotient --> byte (al) remainder --> byte (ah) -------**- divu a,ear 2 *2 1 0 word (a) / byte (ear) quotient --> byte (a) remainder --> byte (ear) -------**- divu a,eam 2+ *3 0 *6 word (a) / byte (eam) quotient --> byte (a) remainder --> byte (eam) -------**- divuw a,ear 2 *4 1 0 long (a) / word (ear) quotient --> word(a) remainder --> word(ear) -------**- divuw a,eam 2+ *5 0 *7 long (a) / word (eam) quotient --> word(a) remainder --> word(eam) -------**- mulu a 1 *8 0 0 byte (ah) * byte (al) --> word (a) ---------- mulu a,ear 2 *9 1 0 byte (a) * byte (ear) --> word (a) ---------- mulu a,eam 2+ *10 0 (b) byte (a) * byte (eam) --> word (a) ---------- muluw a 1 *11 0 0 word (ah) * word (al) --> long (a) ---------- muluw a,ear 2 *12 1 0 word (a) * word (ear) --> long (a) - - -------- muluw a,eam 2+ *13 0 (c) word (a) * word (eam) --> long (a) - - -------- *1: 3: division by 0 7: overflow 15: normal *2: 4: division by 0 8: overflow 16: normal *3: 6+(a): division by 0 9+ (a): overflow 19+(a): normal *4: 4: division by 0 7: overflow 22: normal *5: 6+(a): division by 0 8+ (a): overflow 26+(a): normal *6: (b): division by 0 or overflow 2 x (b): normal *7: (c): division by 0 or overflow 2 x (c): normal *8: 3: byte (ah) is 0. 7: byte (ah) is not 0. *9: 4: byte (ear) is 0. 8: byte (ear) is not 0. *10: 5+(a): byte (eam) is 0, 9+(a): byte (eam) is not 0. *11: 3: word(ah) is 0. 11: word (ah) is not 0. *12: 4: word(ear) is 0. 12: word (ear) is not 0. *13: 5+(a): word (eam) is 0. 13+(a): word (eam) is not 0. note: see table a.5-1 and table a.5-2 for information on (a) to (d) in the table. .com .com .com .com 4 .com u datasheet
599 appendix a instructions table a.8-7 11 signed multiplication/division instructions (word, long word) mnemonic # rg b operation l h a h istnzvc r m w div a 2 *1 0 0 word (ah) / byte (al) quotient --> byte (al) remainder --> byte (ah) z------**- div a,ear 2 *2 1 0 word (a) / byte (ear) quotient --> byte (a) remainder --> byte (ear) z------**- div a,eam 2+ *3 0 *6 word (a) / byte (eam) quotient --> byte (a) remainder --> byte (eam) z------**- divw a,ear 2 *4 1 0 long (a) / word (ear) quotient --> word(a) remainder --> word(ear) -------**- divw a,eam 2+ *5 0 *7 long (a) / word (eam) quotient --> word(a) remainder --> word(eam) -------**- mul a 2 *8 0 0 byte (ah) * byte (al) --> word (a) ---------- mul a,ear 2 *9 1 0 byte (a) * byte (ear) --> word (a) ---------- mul a,eam 2+ *10 0 (b) byte (a) * byte (eam) --> word (a) ---------- mulw a 2 *11 0 0 word (ah) * word (al) --> long (a) ---------- mulw a,ear 2 *12 1 0 word (a) * word (ear) --> long (a) - - -------- mulw a,eam 2+ *13 0 (c) word (a) * word (eam) --> long (a) - - -------- *1: 3: division by 0, 8 or 18: overflow, 18: normal *2: 4: division by 0, 11 or 22: overflow, 23: normal *3: 5+(a): division by 0, 12+(a) or 23+(a): overflow, 24+(a): normal *4: when dividend is positive; 4: division by 0, 12 or 30: overflow, 31: normal when dividend is negative; 4: division by 0, 12 or 31: overflow, 32: normal *5: when dividend is positive; 5+(a): division by 0, 12+(a) or 31+(a): overflow, 32+(a): normal when dividend is negative; 5+(a): division by 0, 12+(a) or 32+(a): overflow, 33+(a): normal *6: (b): division by 0 or overflow, 2 x (b): normal *7: (c): division by 0 or overflow, 2 x (c): normal *8: 3: byte (ah) is 0, 12: result is positive, 13: result is negative *9: 4: byte (ear) is 0, 13: result is positive, 14: result is negative *10: 5+(a): byte (eam) is 0, 14+(a): resu lt is positive, 15+(a): result is negative *11: 3: word(ah) is 0, 16: result is positive, 19: result is negative *12: 4: word(ear) is 0, 17: result is positive, 20: result is negative *13: 5+(a): word(eam) is 0, 18+(a): resu lt is positive, 21+(a): result is negative notes: the execution cycle count found when an overflow occurs in a div or divw instruction may be a pre- operation count or a post-operation count depending on the detection timing. when an overflow occu rs with div or divw instruction, th e contents of the al are destroyed. see table a.5-1 and table a.5-2 for information on (a) to (d) in the table. .com .com .com .com 4 .com u datasheet
600 appendix table a.8-8 39 logic 1 instructions (byte, word) mnemonic # rg b operation l h a h istnzvc r m w and a,#imm8 2 2 0 0 byte (a) <-- (a) and imm8 - - - - - * * r - - and a,ear 2 3 1 0 byte (a) <-- (a) and (ear) - - - - - * * r - - and a,eam 2+ 4+(a) 0 (b) byte (a) <-- (a) and (eam) - - - - - * * r - - and ear,a 2 3 2 0 byte (ear) <-- (ear) and (a) - - - - - * * r - - and eam,a 2+ 5+(a) 0 2 x (b) byte (eam) <-- (eam) and (a) - - - - - * * r - * or a,#imm8 2 2 0 0 byte (a) <-- (a) or imm8 - - - - - * * r - - or a,ear 2 3 1 0 byte (a) <-- (a) or (ear) - - - - - * * r - - or a,eam 2+ 4+(a) 0 (b) byte (a) <-- (a) or (eam) - - - - - * * r - - or ear,a 2 3 2 0 byte (ear) <-- (ear) or (a) - - - - - * * r - - or eam,a 2+ 5+(a) 0 2 x (b) byte (eam) <-- (eam) or (a) - - - - - * * r - * xor a,#imm8 2 2 0 0 byte (a) <-- (a) xor imm8 - - - - - * * r - - xor a,ear 2 3 1 0 byte (a) <-- (a) xor (ear) - - - - - * * r - - xor a,eam 2+ 4+(a) 0 (b) byte (a) <-- (a) xor (eam) - - - - - * * r - - xor ear,a 2 3 2 0 byte (ear) <-- (ear) xor (a) - - - - - * * r - - xor eam,a 2+ 5+(a) 0 2 x (b) byte (eam) <-- (eam) xor (a) - - - - - * * r - * not a 1 2 0 0 byte (a) <-- not (a) - - - - - * * r - - not ear 2 3 2 0 byte (ear) <-- not (ear) - - - - - * * r - - not eam 2+ 5+(a) 0 2 x (b) byte (eam) <-- not (eam) - - - - - * * r - * andw a 1 2 0 0 word (a) <-- (ah) and (a) - - - - - * * r - - andw a,#imm16 3 2 0 0 word (a) <-- (a) and imm16 - - - - - * * r - - andw a,ear 2 3 1 0 word (a) <-- (a) and (ear) - - - - - * * r - - andw a,eam 2+ 4+(a) 0 (c) word (a) <-- (a) and (eam) - - - - - * * r - - andw ear,a 2 3 2 0 word (ear) <-- (ear) and (a) - - - - - * * r - - andw eam,a 2+ 5+(a) 0 2 x (c) word (eam) <-- (eam) and (a) - - - - - * * r - * orw a 1 2 0 0 word (a) <-- (ah) or (a) - - - - - * * r - - orw a,#imm16 3 2 0 0 word (a) <-- (a) or imm16 - - - - - * * r - - orw a,ear 2 3 1 0 word (a) <-- (a) or (ear) - - - - - * * r - - orw a,eam 2+ 4+(a) 0 (c) word (a) <-- (a) or (eam) - - - - - * * r - - orw ear,a 2 3 2 0 word (ear) <-- (ear) or (a) - - - - - * * r - - orw eam,a 2+ 5+(a) 0 2 x (c) word (eam) <-- (eam) or (a) - - - - - * * r - * xorw a 1 2 0 0 word (a) <-- (ah) xor (a) - - - - - * * r - - xorw a,#imm16 3 2 0 0 word (a) <-- (a) xor imm16 - - - - - * * r - - xorw a,ear 2 3 1 0 word (a) <-- (a) xor (ear) - - - - - * * r - - xorw a,eam 2+ 4+(a) 0 (c) word (a) <-- (a) xor (eam) - - - - - * * r - - xorw ear,a 2 3 2 0 word (ear) <-- (ear) xor (a) - - - - - * * r - - xorw eam,a 2+ 5+(a) 0 2 x (c) word (eam) <-- (eam) xor (a) - - - - - * * r - * notw a 1 2 0 0 word (a) <-- not (a) - - - - - * * r - - notw ear 2 3 2 0 word (ear) <-- not (ear) - - - - - * * r - - notw eam 2+ 5+(a) 0 2 x (c) word (eam) <-- not (eam) - - - - - * * r - * note: see table a.5-1 and table a.5-2 for information on (a) to (d) in the table. .com .com .com .com 4 .com u datasheet
601 appendix a instructions table a.8-9 six logic 2 instructions (long word) mnemonic # rg b operation l h a h istnzvc r m w andl a,ear 2 6 2 0 long (a) <-- (a) and (ear) - - - - - * * r - - andl a,eam 2+ 7+(a) 0 (d) long (a) <-- (a) and (eam) - - - - - * * r - - orl a,ear 2 6 2 0 long (a) <-- (a) or (ear) - - - - - * * r - - orl a,eam 2+ 7+(a) 0 (d) long (a) <-- (a) or (eam) - - - - - * * r - - xorl a,ear 2 6 2 0 long (a) <-- (a) xor (ear) - - - - - * * r - - xorl a,eam 2+ 7+(a) 0 (d) long (a) <-- (a) xor (eam) - - - - - * * r - - note: see table a.5-1 and table a.5-2 for information on (a) to (d) in the table. .com .com .com .com 4 .com u datasheet
602 appendix table a.8-10 six sign inversion instructions (byte, word) mnemonic # rg b operation l h a h istnzvc r m w neg a 1 2 0 0 byte (a) <-- 0 - (a) x - - - - * * * * - neg ear 2 3 2 0 byte (ear) <-- 0 - (ear) - - - - - * * * * - neg eam 2+ 5+(a) 0 2 x (b) byte (eam) <-- 0 - (eam) - - - - - * * * * * negw a 1 2 0 0 word (a) <-- 0 - (a) - - - - - * * * * - negw ear 2 3 2 0 word (ear) <-- 0 - (ear) - - - - - * * * * - negw eam 2+ 5+(a) 0 2 x (c) word (eam) <-- 0 - (eam) - - - - - * * * * * note: see table a.5-1 and table a.5-2 for information on (a) to (d) in the table. table a.8-11 one normalization instruction (long word) mnemonic # rg b operation l h a h istnzvc r m w nrml a,r0 2 *1 1 0 long (a) <-- shifts to the position where '1' is set for the first time. byte (rd) <-- shift count at that time ------*--- *1: 4 when all accumulators have a value of 0; otherwise, 6+(r0) .com .com .com .com 4 .com u datasheet
603 appendix a instructions table a.8-12 18 shift instructions (byte, word, long word) mnemonic # rg b operation l h a h istnzvc r m w rorc a 2 2 0 0 byte (a) <-- with right rotation carry - - - - - * * - * - rolc a 2 2 0 0 byte (a) <-- with left rotation carry - - - - - * * - * - rorc ear 2 3 2 0 byte (ear) <-- with right rotation carry - - - - - * * - * - rorc eam 2+ 5+(a) 0 2 x (b) byte (eam) <-- with right rotation carry - - - - - * * - * * rolc ear 2 3 2 0 byte (ear) <-- with left rotation carry - - - - - * * - * - rolc eam 2+ 5+(a) 0 2 x (b) byte (eam) <-- with left rotation carry - - - - - * * - * * asr a,r0 2 *1 1 0 byte (a) <-- arithmetic right shift (a, 1 bit) - - - - - * * - * - lsr a,r0 2 *1 1 0 byte (a) <-- logical right barrel shift (a, r0) - - - - - * * - * - lsl a,r0 2 *1 1 0 byte (a) <-- logical left barrel shift (a, r0) - - - - - * * - * - asrw a 1 2 0 0 word (a) <-- arithmetic right shift (a, 1 bit) - - - - * * * - * - lsrw a/shrw a 1 2 0 0 word (a) <-- logical right shift (a, 1 bit) - - - - * r * - * - lslw a/shlw a 1 2 0 0 word (a) <-- logical left shift (a, 1 bit) - - - - - * * - * - asrw a,r0 2 *1 1 0 word (a) <-- arithmetic right barrel shift (a, r0) - - - - * * * - * - lsrw a,r0 2 *1 1 0 word (a) <-- logical right barrel shift (a, r0) - - - - * * * - * - lslw a,r0 2 *1 1 0 word (a) <-- logical left barrel shift (a, r0) - - - - - * * - * - asrl a,r0 2 *2 1 0 long (a) <-- arithmetic right barrel shift (a, r0) - - - - * * * - * - lsrl a,r0 2 *2 1 0 long (a) <-- logical right barrel shift (a, r0) - - - - * * * - * - lsll a,r0 2 *2 1 0 long (a) <-- logical left barrel shift (a, r0) - - - - - * * - * - *1: 6 when r0 is 0; otherwise, 5 + (r0) *2: 6 when r0 is 0; otherwise, 6 + (r0) note: see table a.5-1 and table a.5-2 for information on (a) to (d) in the table. .com .com .com .com 4 .com u datasheet
604 appendix table a.8-13 31 branch 1 instructions mnemonic # rg b operation l h a h istnzvc r m w bz/beq rel 2 *1 0 0 branch on (z) = 1 ---------- bnz/bne rel 2 *1 0 0 branch on (z) = 0 ---------- bc/blo rel 2 *1 0 0 branch on (c) = 1 ---------- bnc/bhs rel 2 *1 0 0 branch on (c) = 0 ---------- bn rel 2 *1 0 0 branch on (n) = 1 ---------- bp rel 2 *1 0 0 branch on (n) = 0 ---------- bv rel 2 *1 0 0 branch on (v) = 1 ---------- bnv rel 2 *1 0 0 branch on (v) = 0 ---------- bt rel 2 *1 0 0 branch on (t) = 1 ---------- bnt rel 2 *1 0 0 branch on (t) = 0 ---------- blt rel 2 *1 0 0 branch on (v) nor (n) = 1 ---------- bge rel 2 *1 0 0 branch on (v) nor (n) = 0 ---------- ble rel 2 *1 0 0 branch on ((v) xor (n)) or (z) = 1 ---------- bgt rel 2 *1 0 0 branch on ((v) xor (n)) or (z) = 0 ---------- bls rel 2 *1 0 0 branch on (c) or (z) = 1 ---------- bhi rel 2 *1 0 0 branch on (c) or (z) = 0 ---------- bra rel 2 *1 0 0 unconditional branch ---------- jmp @a 1 2 0 0 word (pc) <-- (a) ---------- jmp addr16 3 3 0 0 word (pc) <-- addr16 ---------- jmp @ear 2 3 1 0 word (pc) <-- (ear) ---------- jmp @eam 2+ 4+(a) 0 (c) word (pc) <-- (eam) ---------- jmpp @ear *3 2 5 2 0 word (pc) <-- (ear), (pcb) <-- (ear+2) ---------- jmpp @eam *3 2+ 6+(a) 0 (d) word (pc) <-- (eam), (pcb) <-- (eam+2) ---------- jmpp addr24 4 4 0 0 word(pc) <-- ad24 0-15,(pcb) <-- ad24 16-23 - - -------- call @ear *4 2 6 1 (c) word (pc) <-- (ear) ---------- call addr16 *5 2+ 7+(a) 0 2 x (c)word (pc) <-- (eam) ---------- call @eam *4 3 6 0 (c) word (pc) <-- addr16 ---------- callv #vct4 *5 1 7 0 2 x (c)vector call instruction ---------- callp @ear *6 2 10 2 2 x (c)word(pc) <-- (ear)0-15,(pcb) <-- (ear)16-23 ---------- callp @eam *6 2+ 11+(a) 0 *2 word(pc) < -- (eam)0-15,(pcb) <-- (eam)16-23 - - -------- callp addr24 *7 4 10 0 2 x (c)word(pc) <-- addr0-15, (pcb) <-- addr16-23 ---------- *1: 4 when a branch is made; otherwise, 3 *2: 3 x (c) + (b) *3: read (word) of branch destination address *4: w: save to stack (word) r: read (word) of branch destination address *5: save to stack (word) *6: w: save to stack (long word), r: read (long word) of branch destination address *7: save to stack (long word) note: see table a.5-1 and table a.5-2 for information on (a) to (d) in the table. .com .com .com .com 4 .com u datasheet
605 appendix a instructions table a.8-14 19 branch 2 instructions mnemonic # rg b operation l h a h istnzvc r m w cbne a,#imm8,rel 3 *1 0 0 branch on byte (a) not equal to imm8 ----- ****- cwbne a,#imm16,rel 4 *1 0 0 branch on word (a) not equal to imm16 ----- ****- cbne ear,#imm8,rel 4 *2 1 0 branch on byte (ear) not equal to imm8 ----- ****- cbne eam,#imm8,rel *9 4+ *3 0 (b) branch on byte (eam) not equal to imm8 ----- ****- cwbne ear,#imm16,rel 5 *4 1 0 branch on word (ear) not equal to imm16 ----- ****- cwbne eam,#imm16,rel*9 5+ *3 0 (c) branch on word (eam) not equal to imm16 ----- ****- dbnz ear,rel 3 *5 2 0 branch on byte (ear) = (ear) - 1, (ear)not equal to 0 -----***-- dbnz eam,rel 3+ *6 2 2 x (b)branch on byte (eam) = (eam) - 1, (eam) not equal to 0 -----***-* dwbnz ear,rel 3 *5 2 0 branch on word (ear) = (ear) - 1, (ear) not equal to 0 -----***-- dwbnz eam,rel 3+ *6 2 2 x (c)branch on word (eam) = (eam) - 1, (eam) not equal to 0 -----***-* int #vct8 2 20 0 8 x (c)software interrupt --rs------ int addr16 3 16 0 6 x (c)software interrupt --rs------ intp addr24 4 17 0 6 x (c)software interrupt --rs------ int9 1 20 0 8 x (c)software interrupt --rs------ reti 1 *8 0 *7 return from interrupt - -*******- link #imm8 2 6 0 (c) saves the old frame pointer in the stack upon entering the function, then sets the new frame pointer and reserves the local pointer area. ---------- unlink 1 5 0 (c) recovers the old frame pointer from the stack upon exiting the function. ---------- ret *10 1 4 0 (c) return from subroutine ---------- retp *11 1 6 0 (d) return from subroutine ---------- *1: 5 when a branch is made; otherwise, 4 *2: 13 when a branch is made; otherwise, 12 *3: 7+(a) when a branch is made; otherwise, 6+(a) *4: 8 when a branch is made; otherwise, 7 *5: 7 when a branch is made; otherwise, 6 *6: 8+(a) when a branch is made; otherwise, 7+(a) *7: 3 x (b) + 2 x (c) when jumping to the next interruption request; 6 x (c) when returning from the current interruption *8: 15 when jumping to the next interruption request; 17 when returning from the current interruption *9: do not use rwj+ addressing mode with a cbne or cwbne instruction. *10: return from stack (word) *11: return from stack (long word) note: see table a.5-1 and table a.5-2 for information on (a) to (d) in the table. .com .com .com .com 4 .com u datasheet
606 appendix table a.8-15 28 other control instructions (byte, word, long word) mnemonic # rg b operation l h a h istnzvc r m w pushw a 1 4 0 (c) word (sp) <-- (sp) - 2 , ((sp)) <-- (a) ---------- pushw ah 1 4 0 (c) word (sp) <-- (sp) - 2 , ((sp)) <-- (ah) ---------- pushw ps 1 4 0 (c) word (sp) <-- (sp) - 2 , ((sp)) <-- (ps) ---------- pushw rlst 2 *3 *5 *4 (sp) <-- (sp) - 2n , ((sp)) <-- (rlst) ---------- popw a 1 3 0 (c) word (a) <-- ((sp)) , (sp) <-- (sp) + 2 -*-------- popw ah 1 3 0 (c) word (ah) <-- ((sp)) , (sp) <-- (sp) + 2 ---------- popw ps 1 4 0 (c) word (ps) <-- ((sp)) , (sp) <-- (sp) + 2 - -*******- popw rlst 2 *2 *5 *4 (rlst) <-- ((sp)) , (sp) <-- (sp) ---------- jctx @a 1 14 0 6 x (c)context switch instruction - -*******- and ccr,#imm8 2 3 0 0 byte (ccr) <-- (ccr) and imm8 - -*******- or ccr,#imm8 2 3 0 0 byte(ccr) <-- (ccr) or imm8 - -*******- mov rp,#imm8 2 2 0 0 byte (rp) <-- imm8 ---------- mov ilm,#imm8 2 2 0 0 byte (ilm) <-- imm8 ---------- movea rwi,ear 2 3 1 0 word (rwi) <-- ear ---------- movea rwi,eam 2+ 2+(a) 1 0 word (rwi) <-- eam ---------- movea a,ear 2 1 0 0 word (a) <-- ear -*-------- movea a,eam 2+ 1+(a) 0 0 word (a) <-- eam -*-------- addsp #imm8 2 3 0 0 word (sp) <-- ext(imm8) ---------- addsp #imm16 3 3 0 0 word (sp) <-- imm16 ---------- mov a,brg1 2 *1 0 0 byte (a) <-- (brg1) z * - - - * * - - - mov brg2,a 2 1 0 0 byte (brg2) <-- (a) - - - - - * * - - - nop 1 1 0 0 no operation ---------- adb 1 1 0 0 prefix code for ad space access - - -------- dtb 1 1 0 0 prefix code for dt space access - - -------- pcb 1 1 0 0 prefix code for pc space access ---------- spb 1 1 0 0 prefix code for sp space access ---------- ncc 1 1 0 0 prefix code for flag no-change ---------- cmr 1 1 0 0 prefix code for common register bank ---------- *1: pcb, adb, ssb, usb, spb: 1, dtb, dpr: 2 *2: 7 + 3 x (pop count) + 2 x (pop last register number), 7 when rlst = 0 (no transfer register) *3: 29 + 3 x (push count) - 3 x (push last register number), 8 when rlst = 0 (no transfer register) *4: (pop count) x (c) or (push count) x (c) *5: (pop count) or (push count) note: see table a.5-1 and table a.5-2 for information on (a) to (d) in the table. .com .com .com .com 4 .com u datasheet
607 appendix a instructions table a.8-16 21 bit operand instructions mnemonic # rg b operation l h a h istnzvc r m w movb a,dir:bp 3 5 0 (b) byte (a) <-- ( dir:bp )b z * - - - * * - - - movb a,addr16:bp 4 5 0 (b) byte (a) <-- ( addr16:bp )b z * - - - * * - - - movb a,io:bp 3 4 0 (b) byte (a) <-- ( io:bp )b z * - - - * * - - - movb dir:bp,a 3 7 0 2 x (b) bit ( dir:bp )b <-- (a) - - - - - * * - - * movb addr16:bp,a 4 7 0 2 x (b) bit ( addr16:bp )b <-- (a) - - - - - * * - - * movb io:bp,a 3 6 0 2 x (b) bit ( io:bp )b <-- (a) - - - - - * * - - * setb dir:bp 3 7 0 2 x (b)bit ( dir:bp )b <-- 1 ---------* setb addr16:bp 4 7 0 2 x (b)bit ( addr16:bp )b <-- 1 ---------* setb io:bp 3 7 0 2 x (b)bit ( io:bp )b <-- 1 ---------* clrb dir:bp 3 7 0 2 x (b)bit ( dir:bp )b <-- 0 ---------* clrb addr16:bp 4 7 0 2 x (b)bit ( addr16:bp )b <-- 0 ---------* clrb io:bp 3 7 0 2 x (b)bit ( io:bp )b <-- 0 ---------* bbc dir:bp,rel 4 *1 0 (b) branch on (dir:bp) b = 0 - - ----*--- bbc addr16:bp,rel 5 *1 0 (b) branch on (addr16:bp) b = 0 - - ----*--- bbc io:bp,rel 4 *2 0 (b) branch on (io:bp) b = 0 ------*--- bbs dir:bp,rel 4 *1 0 (b) branch on (dir:bp) b = 1 - - ----*--- bbs addr16:bp,rel 5 *1 0 (b) branch on (addr16:bp) b = 1 - - ----*--- bbs io:bp,rel 4 *1 0 (b) branch on (io:bp) b = 1 ------*--- sbbs addr16:bp,rel 5 *3 0 2 x (b) branch on (addr16:bp) b = 1, bit = 1 - - ----*--* wbts io:bp 3 *4 0 *5 waits until (io:bp) b = 1 ---------- wbtc io:bp 3 *4 0 *5 waits until (io:bp) b = 0 ---------- *1: 8 when a branch is made; otherwise, 7 *2: 7 when a branch is made; otherwise, 6 *3: 10 when the condition is met; otherwise 9 *4: undefined count *5: until the condition is met( dir:bp )b note: see table a.5-1 and table a.5-2 for information on (a) to (d) in the table. table a.8-17 six accumulator operation instructions (byte, word) mnemonic # rg b operation l h a h istnzvc r m w swap 1 3 0 0 byte (a)0-7 <--> (a)8-15 ---------- swapw 1 2 0 0 word (ah) <--> (al) -*-------- ext 1 1 0 0 byte sign extension x - - - - * * - - - extw 1 2 0 0 word sign extension - x - - - * * - - - zext 1 1 0 0 byte zero extension z - - - - r * - - - zextw 1 1 0 0 word zero extensionbyte - z - - - r * - - - .com .com .com .com 4 .com u datasheet
608 appendix table a.8-18 ten string instructions mnemonic # rg b operation l h a hi s t n z vc r m w movs / movsi 2 *2 *5 *3 byte transfer @ah+ <-- @al+, counter = rw0 ---------- movsd 2 *2 *5 *3 byte transfer @ah- <-- @al-, counter = rw0 ---------- sceq / sceqi 2 *1 *5 *4 byte search @ah+ <-- al, counter rw0 ----- ****- sceqd 2 *1 *5 *4 byte search @ah- <-- al, counter rw0 ----- ****- fils / filsi 2 6m+6 *5 *3 byte fill @ah+ <-- al, counter rw0 -----**--- movsw / movswi 2 *2 *5 *6 word transfer @ah+ <-- @al+, counter = rw0 ---------- movswd 2 *2 *5 *6 word transfer @ah- <-- @al-, counter = rw0 ---------- scweq / scweqi 2 *1 *5 *7 word search @ah+ - al, counter = rw0 ----- ****- scweqd 2 *1 *5 *7 word search @ah- - al, counter = rw0 ----- ****- filsw / filswi 2 6m+6 *5 *6 word fill @ah+ <-- al, counter = rw0 -----**--- *1: 5 when rw0 is 0, 4 + 7 x (rw0) when the counter expires, or 7n + 5 when a match occurs *2: 5 when rw0 is 0; otherwise, 4 + 8 x (rw0) *3: (b) x (rw0) + (b) x (rw0) when the source and destinatio n access different areas, calculate the (b) item individually. *4: (b) x n *5: 2 x (rw0) *6: (c) x (rw0) + (c) x (rw0) when the source and destination access different areas, calculate the (c) item individually. *7: (c) x n note: m: rw0 value (counter value), n: loop count see table a.5-1 and table a.5-2 for information on (a) to (d) in the table. .com .com .com .com 4 .com u datasheet
609 appendix a instructions a.9 instruction map each f 2 mc-16lx instruction code consists of 1 or 2 bytes. therefor e, the instruction map consists of multiple pages. tabl e a.9-2 to table a. 9-21 summarize the f 2 mc-16lx instruction map. structure of i nstruction map figure a.9-1 structure of instruction map an instruction such as the nop instruction that ends in one byte is completed within the basic page. an instruction such as the movs instru ction that requires two bytes recogn izes the existence of byte 2 when it references byte 1, and can check th e following one byte by referencing the map for byte 2. figure a.9-2 shows the correspondence between an actual instruction code and instruction map. basic page map bit operation instructions character string operation instructions 2-byte instructions ea instructions x 9 : byte 1 : byte 2 .com .com .com .com 4 .com u datasheet
610 appendix figure a.9-2 correspondence between actual instruction code and instruction map an example of an instruction code is shown in table a.9-1. xy +z uv +w byte 1 byte 2 operand operand . . . [basic page map] [extended page map] (*) length varies depending on the instruction. instruction code some instructions do not contain byte 2. * : the extended page map is a generic name of maps for bit operation instructions, character string operation instructions, 2 -byte instructions, and ea instructions. actually, there are multiple extended page maps for each type of instructions. table a.9-1 example of an instruction code instruction byte 1 (from basic page map) byte 2 (from extended page map) nop 00 + 0 = 00 - and a, #8 30 + 4 = 34 - mov a, adb 60 + f = 6f 00 + 0 = 00 @rw2+d8, #8rel 70 + 0 = 70 f0 + 2 = f2 .com .com .com .com 4 .com u datasheet
611 appendix a instructions table a.9-2 basic page map bit operation instruction character string opera- tion instruction 2-byte instruction ea instruc- tion 1 ea instruc- tion 2 ea instruc- tion 3 ea instruc- tion 4 ea instruc- tion 5 ea instruc- tion 6 ea instruc- tion 7 ea instruc- tion 8 ea instruc- tion 9 ri,ea .com .com .com .com 4 .com u datasheet
612 appendix table a.9-3 bit operation instruction map (first byte = 6c h ) .com .com .com .com 4 .com u datasheet
613 appendix a instructions table a.9-4 character string operation instruction map (first byte = 6e h ) .com .com .com .com 4 .com u datasheet
614 appendix table a.9-5 2-byte instruction map (first byte = 6f h ) mul mulw divu a a a .com .com .com .com 4 .com u datasheet
615 appendix a instructions table a.9-6 ea instruction 1 (first byte = 70 h ) use prohibited use prohibited use prohibited use prohibited use prohibited use prohibited use prohibited use prohibited .com .com .com .com 4 .com u datasheet
616 appendix table a.9-7 ea instruction 2 (first byte = 71 h ) .com .com .com .com 4 .com u datasheet
617 appendix a instructions table a.9-8 ea instruction 3 (first byte = 72 h ) .com .com .com .com 4 .com u datasheet
618 appendix table a.9-9 ea instruction 4 (first byte = 73 h ) .com .com .com .com 4 .com u datasheet
619 appendix a instructions table a.9-10 ea instruction 5 (first byte = 74 h ) .com .com .com .com 4 .com u datasheet
620 appendix table a.9-11 ea instruction 6 (first byte = 75 h ) .com .com .com .com 4 .com u datasheet
621 appendix a instructions table a.9-12 ea instruction 7 (first byte = 76 h ) .com .com .com .com 4 .com u datasheet
622 appendix table a.9-13 ea instruction 8 (first byte = 77 h ) .com .com .com .com 4 .com u datasheet
623 appendix a instructions table a.9-14 ea instruction 9 (first byte = 78 h ) .com .com .com .com 4 .com u datasheet
624 appendix table a.9-15 movea rwi, ea instruction (first byte = 79 h ) .com .com .com .com 4 .com u datasheet
625 appendix a instructions table a.9-16 mov ri, ea instruction (first byte = 7a h ) .com .com .com .com 4 .com u datasheet
626 appendix table a.9-17 movw rwi, ea instruction (first byte = 7b h ) .com .com .com .com 4 .com u datasheet
627 appendix a instructions table a.9-18 mov ea, ri instruction (first byte = 7c h ) .com .com .com .com 4 .com u datasheet
628 appendix table a.9-19 movw ea, rwi instruction (first byte = 7d h ) .com .com .com .com 4 .com u datasheet
629 appendix a instructions table a.9-20 xch ri, ea instruction (first byte = 7e h ) .com .com .com .com 4 .com u datasheet
630 appendix table a.9-21 xchw rwi, ea instruction (first byte = 7f h ) .com .com .com .com 4 .com u datasheet
631 appendix b register index appendix b register index register index table b-1 register index (1/9) address abbreviation of register name register name reset value resource name page number 000000 h (reserved area) * 000001 h pdr1 port 1 data register xxxxxxxx b port 1 163 000002 h pdr2 port 2 data register xxxxxxxx b port 2 168 000003 h pdr3 port 3 data register xxxxxxxx b port 3 173 000004 h pdr4 port 4 data register xxxxxxxx b port 4 178 000005 h pdr5 port5 data register xxxxxxxx b port 5 183 000006 h to 000010 h (reserved area) * 000011 h ddr1 port 1 direction register 00000000 b port 1 163 000012 h ddr2 port 2 direction register 00000000 b port 2 168 000013 h ddr3 port 3 direction register 000x0000 b port 3 173 000014 h ddr4 port 4 direction register xxx00000 b port 4 178 000015 h ddr5 port 5 direction register 00000000 b port 5 183 000016 h to 00001a h (reserved area) * 00001b h ader analog input enable register 11111111 b 8/10-bit a/d converter 362 00001c h to 000025 h (reserved area) * 000026 h smr1 serial mode register 1 00000000 b uart1 387 000027 h scr1 serial control register 1 00000100 b 385 000028 h sidr1/sodr1 serial input data register 1/ serial output data register 1 xxxxxxxx b 391/392 000029 h ssr1 serial status register 1 00001000 b 389 00002a h (reserved area) * 00002b h cdcr1 communication pr escaler control register 1 0xxx0000 b uart1 393 .com .com .com .com 4 .com u datasheet
632 appendix 00002c h to 00002f h (reserved area) * 000030 h enir dtp/external interrupt enable register 00000000 b dtp/external interrupt 333 000031 h eirr dtp/external interrupt factor register xxxxxxxx b 332 000032 h elvr detection level setting register 00000000 b 335 000033 h 00000000 b 334 000034 h adcs a/d control status register 00000000 b 8/10-bit a/d converter 356 000035 h 00000000 b 354 000036 h adcr a/d data register xxxxxxxx b 361 000037 h 00101xxx b 359 000038 h to 00003f h (reserved area) * 000040 h ppgc0 ppg0 operation mode control register 0x000xx1 b 8/16-bit ppg ppg timer 0/1 298 000041 h ppgc1 ppg1 operation mode control register 0x000001 b 300 000042 h ppg01 ppg0/1 count clock select register 000000xx b 302 000043 h (reserved area) * 000044 h ppgc2 ppg2 operation mode control register 0x000xx1 b 8/16-bit ppg timer 2/3 298 000045 h ppgc3 ppg3 operation mode control register 0x000001 b 300 000046 h ppg23 ppg2/3 count clock select register 000000xx b 302 000047 h to 00004f h (reserved area) * table b-1 register index (2/9) address abbreviation of register name register name reset value resource name page number .com .com .com .com 4 .com u datasheet
633 appendix b register index 000050 h ipcp0 input capture data register 0 xxxxxxxx b 16-bit i/o timers 232 000051 h xxxxxxxx b 000052 h ipcp1 input capture data register 1 xxxxxxxx b 232 000053 h xxxxxxxx b 000054 h ics01 input capture control status register 00000000 b 229 000055 h ics23 00000000 b 000056 h tcdt timer counter data register 00000000 b 227 000057 h 00000000 b 000058 h tccs timer counter control status register 00000000 b 225 000059 h (reserved area) * 00005a h ipcp2 input capture data register 2 xxxxxxxx b 16-bit i/o timers 232 00005b h xxxxxxxx b 00005c h ipcp3 input capture data register 3 xxxxxxxx b 232 00005d h xxxxxxxx b 00005e h to 000065 h (reserved area) * 000066 h tmcsr0 timer control status register 00000000 b 16-bit reload timer 0 253 000067 h xxxx0000 b 251 000068 h tmcsr1 00000000 b 16-bit reload timer 1 253 000069 h xxxx0000 b 251 00006a h to 00006e h (reserved area) * 00006f h romm rom mirroring function select register xxxxxxx1 b rom mirroring function select module 526 000070 h to 00007f h (reserved area) * 000080 h bvalr message buffer valid register 00000000 b can controller 450 000081 h (reserved area) * 000082 h treqr transmission request register 00000000 b can controller 454 table b-1 register index (3/9) address abbreviation of register name register name reset value resource name page number .com .com .com .com 4 .com u datasheet
634 appendix 000083 h (reserved area) * 000084 h tcanr transmission cancel register 00000000 b can controller 460 000085 h (reserved area) * 000086 h tcr transmission complete register 00000000 b can controller 462 000087 h (reserved area) * 000088 h rcr reception complete register 00000000 b can controller 466 000089 h (reserved area) * 00008a h rrtrr reception rtr register 00000000 b can controller 468 00008b h (reserved area) * 00008c h rovrr reception overrun register 00000000 b can controller 470 00008d h (reserved area) * 00008e h rier reception complete interrupt enable register 00000000 b can controller 472 00008f h to 00009d h (reserved area) * 00009e h pacsr address detection control register 00000000 b address match detecting function 511 00009f h dirr delayed interrupt request generate/cancel register xxxxxxx0 b delayed interrupt generation module 323 0000a0 h lpmcr low-power consumption mode control register 00011000 b low-power consumption mode 130 0000a1 h ckscr clock select register 11111100 b clock 115 0000a2 h to 0000a7 h (reserved area) * 0000a8 h wdtc watchdog timer control register xxxxx111 b watchdog timer 208 0000a9 h tbtc timebase timer control register 1xx00100 b timebase timer 193 0000aa h wtc watch timer control register 1x001000 b watch timer 279 0000ab h to 0000ad h (reserved area) * 0000ae h fmcs flash memory control status register 000x0000 b 512-kbit flash memory 530 0000af h (reserved area) * table b-1 register index (4/9) address abbreviation of register name register name reset value resource name page number .com .com .com .com 4 .com u datasheet
635 appendix b register index 0000b0 h icr00 interrupt control register 00 00000111 b interrupt controller 66 0000b1 h icr01 interrupt control register 01 00000111 b 0000b2 h icr02 interrupt control register 02 00000111 b 0000b3 h icr03 interrupt control register 03 00000111 b 0000b4 h icr04 interrupt control register 04 00000111 b 0000b5 h icr05 interrupt control register 05 00000111 b 0000b6 h icr06 interrupt control register 06 00000111 b 0000b7 h icr07 interrupt control register 07 00000111 b 0000b8 h icr08 interrupt control register 08 00000111 b 0000b9 h icr09 interrupt control register 09 00000111 b 0000ba h icr10 interrupt control register 10 00000111 b 0000bb h icr11 interrupt control register 11 00000111 b 0000bc h icr12 interrupt control register 12 00000111 b 0000bd h icr13 interrupt control register 13 00000111 b 0000be h icr14 interrupt control register 14 00000111 b 0000bf h icr15 interrupt control register 15 00000111 b 0000c0 h to 0000ff h (reserved area) * 001ff0 h padr0 detect address setting register 0 (low) xxxxxxxx b address match detecting function 513 001ff1 h detect address setting register 0 (middle) xxxxxxxx b 001ff2 h detect address setting register 0 (high) xxxxxxxx b 001ff3 h padr1 detect address setting register 1 (low) xxxxxxxx b 513 001ff4 h detect address setting register 1 (middle) xxxxxxxx b 001ff5 h detect address setting register 1 (high) xxxxxxxx b 003900 h tmr0/tmrlr0 16-bit timer register 0/ 16-bit reload register 0 xxxxxxxx b 16-bit reload timer 0 255/256 003901 h xxxxxxxx b table b-1 register index (5/9) address abbreviation of register name register name reset value resource name page number .com .com .com .com 4 .com u datasheet
636 appendix 003902 h tmr1/tmrlr1 16-bit timer register 1/ 16-bit reload register 1 xxxxxxxx b 16-bit reload timer 1 255/256 003903 h xxxxxxxx b 003904 h to 00390f h (reserved area) * 003910 h prll0 ppg0 reload register l xxxxxxxx b 8/16-bit ppg timer 304 003911 h prlh0 ppg0 reload register h xxxxxxxx b 304 003912 h prll1 ppg1 reload register l xxxxxxxx b 304 003913 h prlh1 ppg1 reload register h xxxxxxxx b 304 003914 h prll2 ppg2 reload register l xxxxxxxx b 304 003915 h prlh2 ppg2 reload register h xxxxxxxx b 304 003916 h prll3 ppg3 reload register l xxxxxxxx b 304 003917 h prlh3 ppg3 reload register h xxxxxxxx b 304 003918 h to 00392f h (reserved area) * 003930 h to 003bff h (reserved area) * 003c00 h to 003c0f h ram (general-purpose ram) 003c10 h to 003c13 h idr0 id register 0 xxxxxxxx b to xxxxxxxx b can controller 479 003c14 h to 003c17 h idr1 id register 1 xxxxxxxx b to xxxxxxxx b 479 003c18 h to 003c1b h idr2 id register 2 xxxxxxxx b to xxxxxxxx b 479 003c1c h to 003c1f h idr3 id register 3 xxxxxxxx b to xxxxxxxx b 479 003c20 h to 003c23 h idr4 id register 4 xxxxxxxx b to xxxxxxxx b 479 table b-1 register index (6/9) address abbreviation of register name register name reset value resource name page number .com .com .com .com 4 .com u datasheet
637 appendix b register index 003c24 h to 003c27 h idr5 id register 5 xxxxxxxx b to xxxxxxxx b can controller 479 003c28 h to 003c2b h idr6 id register 6 xxxxxxxx b to xxxxxxxx b 479 003c2c h to 003c2f h idr7 id register 7 xxxxxxxx b to xxxxxxxx b 479 003c30 h 003c31 h dlcr0 dlc register 0 xxxxxxxx b xxxxxxxx b 482 003c32 h 003c33 h dlcr1 dlc register 1 xxxxxxxx b xxxxxxxx b 482 003c34 h 003c35 h dlcr2 dlc register 2 xxxxxxxx b xxxxxxxx b 482 003c36 h 003c37 h dlcr3 dlc register 3 xxxxxxxx b xxxxxxxx b 482 003c38 h 003c39 h dlcr4 dlc register 4 xxxxxxxx b xxxxxxxx b 482 003c3a h 003c3b h dlcr5 dlc register 5 xxxxxxxx b xxxxxxxx b 482 003c3c h 003c3d h dlcr6 dlc register 6 xxxxxxxx b xxxxxxxx b 482 003c3e h 003c3f h dlcr7 dlc register 7 xxxxxxxx b xxxxxxxx b 482 003c40 h to 003c47 h dtr0 data register 0 xxxxxxxx b to xxxxxxxx b 483 003c48 h to 003c4f h dtr1 data register 1 xxxxxxxx b to xxxxxxxx b 483 003c50 h to 003c57 h dtr2 data register 2 xxxxxxxx b to xxxxxxxx b 483 003c58 h to 003c5f h dtr3 data register 3 xxxxxxxx b to xxxxxxxx b 483 table b-1 register index (7/9) address abbreviation of register name register name reset value resource name page number .com .com .com .com 4 .com u datasheet
638 appendix 003c60 h to 003c67 h dtr4 data register 4 xxxxxxxx b to xxxxxxxx b can controller 483 003c68 h to 003c6f h dtr5 data register 5 xxxxxxxx b to xxxxxxxx b 483 003c70 h to 003c77 h dtr6 data register 6 xxxxxxxx b to xxxxxxxx b 483 003c78 h to 003c7f h dtr7 data register 7 xxxxxxxx b to xxxxxxxx b 483 003c80 h to 003cff h (reserved area) * 003d00 h 003d01 h csr control status register 0xxxx001 b 00xxx000 b can controller 437/439 003d02 h leir last event indicate register 000xx000 b 442 003d03 h (reserved area) * 003d04 h 003d05 h rtec receive/transmit error counter 00000000 b 00000000 b can controller 444 003d06 h 003d07 h btr bit timing register 11111111 b x1111111 b 446 003d08 h ider ide register xxxxxxxx b 452 003d09 h (reserved area) * 003d0a h trtrr transmission rtr register 00000000 b can controller 456 003d0b h (reserved area) * 003d0c h rfwtr remote frame receiving wait register xxxxxxxx b can controller 458 003d0d h (reserved area) * 003d0e h tier transmission complete interrupt enable register 00000000 b can controller 464 003d0f h (reserved area) * 003d10 h 003d11 h amsr acceptance mask select register xxxxxxxx b to xxxxxxxx b can controller 474 table b-1 register index (8/9) address abbreviation of register name register name reset value resource name page number .com .com .com .com 4 .com u datasheet
639 appendix b register index 003d12 h 003d13 h (reserved area) * 003d14 h to 003d17 h amr0 acceptance mask register 0 xxxxxxxx b to xxxxxxxx b can controller 476 003d18 h to 003d1b h amr1 acceptance mask register 1 xxxxxxxx b to xxxxxxxx b 476 003d1c h to 003dff h (reserved area) * 003e00 h to 003eff h (reserved area) * 003ff0 h to 003fff h (reserved area) * explanation of reset value 0: the reset value of this bit is 0. 1: the reset value of this bit is 1. x: the reset value of this bit is unfixed. * : do not write the data to "(reserved area)". if the da ta is read from "(reserved area)", it is undefined values. table b-1 register index (9/9) address abbreviation of register name register name reset value resource name page number .com .com .com .com 4 .com u datasheet
640 appendix appendix c pin function index pin function index table c-1 pin function index (1/2) pin number pin name circuit ty p e function page number for function explanation page number for block diagram m05 1 av cc ? v cc input pin for a/d converter 350 349 2avr ? vref + input pin for a/d converter 350 349 3 to 10 p50 to p57 e general-purpose i/o ports 181 182 an0 to an7 analog input pins for a/d converter 350 349 11 p37 d general-purpose i/o port 171 172 adtg external trigger input pin for a/d converter 352 349 12 p20 d general-purpose i/o port 166 167 tin0 event input pin for reload timer 0 248 246 13 p21 d general-purpose i/o port 166 167 tot0 event output pin for reload timer 0 248 246 14 p22 d general-purpose i/o port 166 167 tin1 event input pin for reload timer 1 248 246 15 p23 d general-purpose i/o ports 166 167 tot1 event output pin for reload timer 1 248 246 16 to 19 p24 to p27 d general-purpose i/o ports 166 167 int4 to int7 external interrupt input pins 331 329 20 md2 f operation mode select input pin 150 ? 21 md1 c operation mode select input pin 150 ? 22 md0 c operation mode select input pin 150 ? 23 rst b external reset input pin 103 103 24 v cc power (5 v) input pin ?? 25 v ss ? power (0 v) input pin ?? 26 c ? power stabilization capacitance pin ?? 27 x0 a high-speed oscillation pin 109 112 28 x1 a high-speed oscillation pin 109 112 29 to 32 p10 to p13 d general-purpose i/o ports 161 162 in0 to in3 trigger input pins for input capture channels 0 to 3 222 220 33 to 36 p14 to p17 d general-purpose i/o ports 161 162 ppg0 to ppg3 output pins for ppg timers 01 and 23 296 290/293 .com .com .com .com 4 .com u datasheet
641 appendix c pin function index 37 p40 d general-purpose i/o port 176 177 sin1 serial data input pin for uart1 383 380 38 p41 d general-purpose i/o port 176 177 sck1 serial clock input/output pin for uart1 383 380 39 p42 d general-purpose i/o port 176 177 sot1 serial data output pin for uart1 383 380 40 p43 d general-purpose i/o port 176 177 tx transmit output pin for can controller 433 429 41 p44 d general-purpose i/o port 176 177 rx receive input pin for can controller 433 429 42 to 45 p30 to p33 d general-purpose i/o port 171 172 46 x0a* a low-speed oscillation pin 109 112 p35* general-purpose i/o port 171 172 47 x1a* a low-speed oscillation pin 109 112 p36* general-purpose i/o port 171 172 48 av ss ? v ss input pin for a/d converter 350 349 *:mb90387, mb90f387: x1a, x0a mb90387s, mb90f387s: p36, p35 table c-1 pin function index (2/2) pin number pin name circuit ty p e function page number for function explanation page number for block diagram m05 .com .com .com .com 4 .com u datasheet
642 appendix appendix d interrupt vector index interrupt vector index table d-1 interrupt vector index (1/2) interrupt number interrupt factor interrupt control address in vector table page number icr address low middle high #08 reset ?? ffffdc h ffffdd h ffffde h 99 #09 int9 instruction ?? ffffd8 h ffffd9 h ffffda h 508 #10 exception processing ?? ffffd4 h ffffd5 h ffffd6 h 91 #11 can controller receive completion icr00 0000b0 h ffffd0 h ffffd1 h ffffd2 h 484 #12 can controller receive completion/ node status transition ffffcc h ffffcd h ffffce h 484 #13 reserved icr01 0000b1 h ffffc8 h ffffc9 h ffffca h ? #14 reserved ffffc4 h ffffc5 h ffffc6 h ? #15 can wake-up icr02 0000b2 h ffffc0 h ffffc1 h ffffc2 h 62 #16 timebase timer ffffbc h ffffbd h ffffbe h 195 #17 16-bit reload timer 0 icr03 0000b3 h ffffb8 h ffffb9 h ffffba h 257 #18 8/10-bit a/d converter ffffb4 h ffffb5 h ffffb6 h 364 #19 16-bit free-run timer overflow icr04 0000b4 h ffffb0 h ffffb1 h ffffb2 h 233 #20 reserved ffffac h ffffad h ffffae h ? #21 reserved icr05 0000b5 h ffffa8 h ffffa9 h ffffaa h ? #22 ppg timer channel 0/1 underflow ffffa4 h ffffa5 h ffffa6 h 305 #23 input capture 0 fetched icr06 0000b6 h ffffa0 h ffffa1 h ffffa2 h 233 #24 external interrupt 4 (int4)/ external interrupt 5 (int5) ffff9c h ffff9d h ffff9e h 328 #25 input capture 1 fetched icr07 0000b7 h ffff98 h ffff99 h ffff9a h 233 #26 ppg timer channel 2/3 underflow ffff94 h ffff95 h ffff96 h 305 #27 external interrupt 6 (int6)/ external interrupt 7 (int7) icr08 0000b8 h ffff90 h ffff91 h ffff92 h 328 #28 watch timer ffff8c h ffff8d h ffff8e h 281 .com .com .com .com 4 .com u datasheet
643 appendix d interrupt vector index #29 reserved icr09 0000b9 h ffff88 h ffff89 h ffff8a h ? #30 input capture 2 fetched input capture 3 fetched ffff84 h ffff85 h ffff86 h 233 #31 reserved icr10 0000ba h ffff80 h ffff81 h ffff82 h ? #32 reserved ffff7c h ffff7d h ffff7e h ? #33 reserved icr11 0000bb h ffff78 h ffff79 h ffff7a h ? #34 reserved ffff74 h ffff75 h ffff76 h ? #35 reserved icr12 0000bc h ffff70 h ffff71 h ffff72 h ? #36 16-bit reload timer 1 ffff6c h ffff6d h ffff6e h 257 #37 uart1 receive icr13 0000bd h ffff68 h ffff69 h ffff6a h 395 #38 uart1 transmit ffff64 h ffff65 h ffff66 h 395 #39 reserved icr14 0000be h ffff60 h ffff61 h ffff62 h ? #40 reserved ffff5c h ffff5d h ffff5e h ? #41 flash memory icr15 0000bf h ffff58 h ffff59 h ffff5a h 528 #42 delayed interrupt generation module ffff54 h ffff55 h ffff56 h 320 table d-1 interrupt vector index (2/2) interrupt number interrupt factor interrupt control address in vector table page number icr address low middle high .com .com .com .com 4 .com u datasheet
644 appendix .com .com .com .com 4 .com u datasheet
645 index the index follows on the next page. this is listed in alphabetic order. .com .com .com .com 4 .com u datasheet
646 index index numerics 16-bit free-run timer block diagram of 16-bit free-run timer ........... 218 operation of 16-bit free-run timer ................... 234 operation timing of 16-bit free-run timer ........ 235 setting of 16-bit free-run timer ....................... 234 16-bit input/output timer 16-bit input/output timer interrupts and ei 2 os function ............................................ 233 block diagram of 16-bit input/output timer ......................................................... 217 block diagram of pins for 16-bit input/output timer ......................................................... 222 configuration of 16-bit input/output timer ....... 216 correspondence between 16-bit input/output timer interrupt and ei 2 os ............................ 233 functions of 16-bit input/output timer ............. 216 generation of interrupt request from 16-bit input/output timer ................... 224 interrupt control bits an d interrupt factors of 16-bit input/output timer ................... 233 list of registers and reset values of 16-bit input/output timer ................... 223 pins of 16-bit input/output timer ..................... 222 precautions when 16-b it input/output timer ...... 239 16-bit ppg output operation mode setting for 16-bit ppg output operation mode ......................................................... 310 16-bit reload registers 16-bit reload registers (tmrlr0,tmrlr1) ......................................................... 256 16-bit reload timer baud rate by internal timer (16-bit reload timer output) .............. 405 block diagram for pins of 16-bit reload timer ......................................................... 248 block diagram of 16-bit reload timer .............. 246 correspondence between 16-bit reload timer interrupt and ei 2 os ............................ 257 ei 2 os function of 16-bit reload timer ............. 257 generation of interrupt request from 16-bit reload timer ........................... 250 interrupts of 16-bit reload timer ...................... 257 list of registers and reset values of 16-bit reload timer ........................... 249 operation modes of 16-bit reload timer ........... 244 pins of 16-bit reload timer ............................. 248 precautions when using 16-bit reload timer ......................................................... 268 setting of 16-bit reload timer ......................... 258 16-bit timer register 16-bit timer registers (tmr0,tmr1) ..............255 operating state of 16-bit timer register ............259 operation as 16-bit time r register underflows .................................................261, 266 24-bit operand linear addressing by specifying 24-bit operand ...........................................................28 2-channel independent operation mode setting for 8-bit ppg output 2-channel independent operation mode ..................................308 32-bit register addressing by indirect-specifying 32-bit register ...........................................................28 512 kbit flash memory features of 512 kbit flash memory ...................528 overview of 512 kbit flash memory .................528 program example of 512 kbit flash memory .....553 sector configuration of 512 kbit flash memory .........................................................529 8+8-bit ppg output operation mode setting for 8+8-bit ppg output operation mode .........................................................313 8-/10-bit a/d converter 8-/10-bit a/d converter interrupt and ei 2 os .........................................................364 a/d-converted data protection function in 8-/10-bit a/d converter ...................373 block diagram of 8-/10-bit a/d converter .........349 conversion modes of 8-/10-bit a/d converter .........................................................348 ei 2 os function of 8-/10-bit a/d converter ........364 function of 8-/10-bit a/d converter ..................348 generation of interrupt from 8-/10-bit a/d converter .........................................................353 list of registers and reset values of 8-/10-bit a/d converter .......................353 pins of 8-/10-bit a/d converter ........................352 precautions when using 8-/10-bit a/d converter .........................................................375 8-/16-bit ppg timer 8-/16-bit ppg timer interrupt and ei 2 os function .........................................................306 block diagram of 8-/16-bit ppg timer 0 ...........290 block diagram of 8-/16-bit ppg timer 1 ...........293 block diagram of 8-/16-bit ppg timer pins .......296 correspondence between 8-/16-bit ppg timer interrupt and ei 2 os ............................305 functions of 8-/16-bit ppg timer ......................286 .com .com .com .com 4 .com u datasheet
647 index generation of interrupt request from 8-/16-bit ppg timer ............................297 interrupts of 8-/16-bit ppg timer ......................305 list of registers and reset values of 8-/16-bit ppg timer ............................297 operation modes of 8-/16-bit ppg timer ...........286 operation of 8-/16-bit ppg timer ......................307 pins of 8-/16-bit ppg timer ..............................296 precautions when using 8-/16-bit ppg timer ..........................................................316 8-bit ppg output setting for 8-bit ppg output 2-channel independent operation mode ..................................308 a a accumulator (a) ............................................... 36 a/d control status register a/d control status register (high) (adcs: h) ......................................................... 354 a/d control status register (low) (adcs: l) ......................................................... 356 a/d converter 8-/10-bit a/d converter interrupt and ei 2 os ......................................................... 364 a/d-converted data protection function in 8-/10-bit a/d converter ................... 373 block diagram of 8-/10-bit a/d converter ........ 349 conversion modes of 8-/10-bit a/d converter ......................................................... 348 ei 2 os function of 8-/10-bit a/d converter ....... 364 function of 8-/10-bit a/d converter .................. 348 generation of interrupt from 8-/10-bit a/d converter ......................................................... 353 interrupt of a/d converter ............................... 364 list of registers and reset values of 8-/10-bit a/d converter ...................... 353 pins of 8-/10-bit a/d converter ........................ 352 precautions when using 8-/10-bit a/d converter ......................................................... 375 a/d data register a/d data register (high) (adcr: h) ............... 359 a/d data register (low) (adcr: l) ................ 361 a/d-converted data a/d-converted data protection function in 8-/10-bit a/d converter ................... 373 acceptance mask register acceptance mask register (amr) .................... 476 acceptance mask select register acceptance mask select register (amsr) ........ 474 access space bank registers and access space ........................ 29 accumulator accumulator (a) ............................................... 36 adb additional bank register (adb) ........................ 49 bank select prefix (pcb,dtb,adb,spb) ........... 53 adcr a/d data register (high) (adcr: h) ............... 359 a/d data register (low) (adcr: l) ................ 361 adcs a/d control status register (high) (adcs: h) ......................................................... 354 a/d control status register (low) (adcs: l) ......................................................... 356 continuous conversion mode (adcs: md1,md0= "10 b ") ................ 365 .com .com .com .com 4 .com u datasheet
648 index pause-conversion mode (adcs: md1,md0= "11 b " ) ......................................................... 365 single conversion mode (adcs: md1,md0= "00 b " or "01 b ") .................................. 365 additional bank register additional bank register (adb) ........................ 49 address effective address field ............................ 573, 590 address detection control register address detection control register (pacsr) ......................................................... 511 address match detection function block diagram of address match detection function ......................................................... 509 list of registers and reset values of address match detection function .................. 510 operation of address match detection function ......................................................... 515 operation of address match detection function at storing patch program in e 2 prom ......................................................... 519 overview of address match detection function ......................................................... 508 program example for address match detection function ............................................ 521 addressing addressing ..................................................... 572 addressing by indirect-specifying 32-bit register ........................................................... 28 bank addressing and default space .................... 30 direct addressing ............................................ 574 indirect addressing ......................................... 580 linear addressing and bank addressing ............. 27 ader analog input enable register (ader) .............. 362 all data erase all data erase from flash memory (chip erase) ......................................................... 548 amr acceptance mask register (amr) .................... 476 amsr acceptance mask select register (amsr) ........ 474 analog input enable register analog input enable register (ader) .............. 362 array array of prefix codes ........................................ 58 asynchronous mode operation in asynchronous mode ..................... 410 b bank access to ff bank by rom mirroring function ......................................................... 524 register bank ................................................... 51 setting of each bank and data access .................49 bank addressing bank addressing and default space ....................30 linear addressing and bank addressing ..............27 bank registers bank registers and access space ........................29 bank select prefix bank select prefix (pcb,dtb,adb,spb) ...........53 bap buffer address pointer (bap) .............................86 basic configuration basic configuration of serial programming connection for mb90f387/s ...............558 baud rate baud rate by dedicated baud rate generator .........................................................402 baud rate by external clock ............................407 baud rate by internal timer (16-bit reload timer output) ...............405 select of uart1 baud rate .............................400 bidirectional communication bidirectional communication function ..............418 bit timing calculation of bit timing .................................448 bit timing register bit timing register (btr) ...............................446 bit timing segment definition of bit timing segment .....................447 block diagram block diagram for pins of 16-bit reload timer .........................................................248 block diagram for pins of can controller ........433 block diagram of 16-bit free-run timer ............218 block diagram of 16-bit input/output timer ......217 block diagram of 16-bit reload timer ..............246 block diagram of 8-/10-bit a/d converter .........349 block diagram of 8-/16-bit ppg timer 0 ...........290 block diagram of 8-/16-bit ppg timer 1 ...........293 block diagram of 8-/16-bit ppg timer pins .......296 block diagram of address match detection function .........................................................509 block diagram of can controller ....................429 block diagram of clock generation section ......112 block diagram of delayed interrupt generation module ..............................................321 block diagram of dtp/external interrupt ..........329 block diagram of external reset pin .................103 block diagram of input capture ........................220 block diagram of low-power consumption circuit .........................................................127 block diagram of mb90385 series .......................8 block diagram of pins .....................................331 block diagram of pins for 16-bit input/output timer .........................................................222 .com .com .com .com 4 .com u datasheet
649 index block diagram of pins of port 2 (general-purpose i/o port) ...................167 block diagram of pins of port 3 ........................172 block diagram of pins of port 4 ........................177 block diagram of pins of port 5 ........................182 block diagram of pins of uart1 .....................383 block diagram of port 1 pins (in single chip mode) ..........................................................162 block diagram of rom mirroring function select module .....................................524 block diagram of timebase timer ....................190 block diagram of uart1 ................................380 block diagram of watch timer .........................276 block diagram of watchdog timer ...................205 details of pins in block diagram ...............218, 221 btr bit timing register (btr) ...............................446 buffer address pointer buffer address pointer (bap) .............................86 bus mode bus mode ........................................................154 bval caution for disabling message buffers by bval bits ..........................................................503 bvalr message buffer valid register (bvalr) ..........450 c can program example of can transmission and reception ...........................................504 can controller block diagram for pins of can controller ........433 block diagram of can controller ....................429 can controller registers .................................434 explanation of operation of can controller ......486 generation of interrupt request by can controller ..........................................................436 interrupts of can controller ............................484 overview of can controller ............................428 pins of can controller ....................................433 registers and vector tables related to interrupt of can controller .................................485 ccr configuration of condition code register (ccr) ............................................................43 cdcr communication prescaler control register 1 (cdcr1) ............................................393 channels channels and ppg pins of ppg timers ..............289 chip erase all data erase from flash memory (chip erase) ..........................................................548 circuit block diagram of low-power consumption circuit ......................................................... 127 ckscr configuration of clock select register (ckscr) ......................................................... 115 clock baud rate by external clock ............................ 407 block diagram of clock generation section ...... 112 clock .............................................................. 109 clock supply map ........................................... 110 connection of oscillator and external clock ...... 123 machine clock ................................................ 119 oscillation clock frequency and serial clock input frequency ............... 560 register in clock generation section and list of reset values ...................................... 114 setting operation clock of watchdog timer ......................................................... 283 supply of operation clock ............................... 199 clock generation block diagram of clock generation section ......................................................... 112 register in clock generation section and list of reset values ............................ 114 clock mode clock mode ............................................ 118, 125 transition of clock mode ......................... 118, 147 clock select register configuration of clock select register (ckscr) ......................................................... 115 clock supply clock supply .................................................. 189 cycle of clock supply ..................................... 275 clock synchronous mode operation in clock synchronous mode (operation mode 2) ............................ 415 cmr common register bank prefix (cmr) ................ 55 command sequence command sequence table ............................... 533 common register bank prefix common register bank prefix (cmr) ................ 55 communication bidirectional communication function .............. 418 master/slave type communication function ......................................................... 420 communication prescaler control register communication prescaler control register 1 (cdcr1) ........................................... 393 condition code register configuration of condit ion code register (ccr) ........................................................... 43 .com .com .com .com 4 .com u datasheet
650 index connection example of minimum connection to flash microcontroller programmer (power supplied from flash microcontroller programmer) ...................................... 567 example of minimum connection to flash microcontroller programmer (user power supply used) .................. 565 connection example connection example in single-chip mode (power supplied from flash microcontroller programmer) ...................................... 563 connection example in single-chip mode (user power supply used) .................. 561 consumption block diagram of low-power consumption circuit ......................................................... 127 cpu operation modes and current consumption ......................................................... 124 continuous conversion mode continuous conversion mode (adcs: md1,md0= "10 b ") ............... 365 operation of continuous conversion mode ......................................................... 368 continuous conversion mode setting of continuous conversion mode ............ 368 control status register control status register (high) (csr: h) ........... 437 control status register (low) (csr: l) ............ 439 conversion conversion using ei 2 os ................................. 372 conversion mode continuous conversion mode (adcs: md1,md0= "10 b ") ............... 365 conversion modes of 8-/10-bit a/d converter ......................................................... 348 operation of continuous conversion mode ......................................................... 368 operation of pause-conversion mode ................ 370 operation of single conversion mode ............... 366 pause-conversion mode (adcs: md1,md0= "11 b ") ......................................................... 365 setting of continuous conversion mode ............ 368 setting of pause-conversion mode .................... 370 setting of single conversion mode ................... 366 single conversion mode (adcs: md1,md0= "00 b " or "01 b ") .................................. 365 count clock select register ppg0/1 count clock sel ect register (ppg01) ......................................................... 302 cpu cpu and resources for mb90385 series ............... 6 cpu intermittent operation mode cpu intermittent operation mode .................... 125 operation in cpu intermittent operation mode .........................................................133 cpu operation modes cpu operation modes and current consumption .........................................................124 csr control status register (high) (csr: h) ............437 control status register (low) (csr: l) .............439 current consumption cpu operation modes and current consumption .........................................................124 cycle cycle of clock supply ......................................275 processing of program fo r measuring cycle using input capture ......................................240 d data access setting of each bank and data access .................49 data bank register data bank register (dtb) ..................................49 data counter data counter (dct) ...........................................84 data polling flag data polling flag (dq7) ...................................537 data programming data programming procedure ...........................546 data programming to flash memory .................546 data register data register (dtr) ........................................483 dct data counter (dct) ...........................................84 dedicated baud rate generator baud rate by dedicated baud rate generator .........................................................402 dedicated registers configuration of dedicated registers ...................33 dedicated registers and general-purpose register ...........................................................35 default space bank addressing and default space ....................30 delayed interrupt generation module block diagram of delayed interrupt generation module ..............................................321 explanation of operation of delayed interrupt generation module .............................324 list of registers and reset values in delayed interrupt generation module ................322 overview of delayed interrupt generation module .........................................................320 precautions when using dela yed interrupt generation module ..............................................325 program example of delayed interrupt generation module ..............................................326 .com .com .com .com 4 .com u datasheet
651 index delayed interrupt request generate/cancel register delayed interrupt request generate/cancel register (dirr) ...............................................323 descriptor configuration of ei 2 os descriptor (isd) .............82 detect address setting detect address .....................................515 detect address setting registers detect address setting registers (padr0 and padr1) ............................................513 functions of detect address setting registers ..........................................................514 detection level setting register detection level setting register (elvr) (high) ..........................................................334 detection level setting register (elvr) (low) ..........................................................335 direct addressing direct addressing ............................................574 direct page register direct page register (dpr) ................................48 dirr delayed interrupt request generate/cancel register (dirr) ...............................................323 disabling message buffers caution for disabling message buffers by bval bits ..........................................................503 dlc register dlc register (dlcr) ......................................482 dlcr dlc register (dlcr) ......................................482 dpr direct page register (dpr) ................................48 dq2 toggle bit flag (dq2) .....................................542 dq3 sector erase timer flag (dq3) .........................541 dq5 timing limit over flag (dq5) .........................540 dq6 toggle bit flag (dq6) .....................................539 dq7 data polling flag (dq7) ...................................537 dtb bank select prefix (pcb,dtb,adb,spb) ............53 data bank register (dtb) ..................................49 dtp function dtp function ..................................................340 program example of dtp function ...................344 dtp/external interrupt block diagram of dtp/external interrupt ..........329 dtp/external interrupt operation ......................337 list of registers and reset values in dtp/external interrupt ....................331 pins of dtp/external interrupt .......................... 331 precautions when using dt p/external interrupt ......................................................... 341 program example of dtp/external interrupt function ......................................................... 343 setting of dtp/external interrupt ...................... 336 dtp/external interrupt enable register dtp/external interrupt enable register (enir) ......................................................... 333 dtp/external interrupt factor register dtp/external interrupt factor register (eirr) ......................................................... 332 dtp/external interrupt function dtp/external interrupt function ....................... 328 dtr data register (dtr) ........................................ 483 e e 2 prom e 2 prom memory map .................................... 517 system configuration and e 2 prom memory map ......................................................... 516 effective address effective address field ............................ 573, 590 ei 2 os 16-bit input/output timer interrupts and ei 2 os function ............................................ 233 8-/10-bit a/d converter interrupt and ei 2 os ......................................................... 364 8-/16-bit ppg timer interrupt and ei 2 os function ......................................................... 306 conversion using ei 2 os .................................. 372 correspondence between 16-bit input/output timer interrupt and ei 2 os ............................ 233 correspondence between 16-bit reload timer interrupt and ei 2 os ............................ 257 correspondence between 8-/16-bit ppg timer interrupt and ei 2 os ............................ 305 correspondence between timebase timer interrupt and ei 2 os .......................................... 195 ei 2 os ............................................................... 80 ei 2 os function of 16-bit reload timer ............. 257 ei 2 os function of 8-/10-bit a/d converter ....... 364 ei 2 os function of uart1 ............................... 396 ei 2 os processing time (time for one transfer) ........................................................... 89 interrupt related to uart1 and ei 2 os ............. 396 operation of ei 2 os ...................................... 81, 87 procedure for use of ei 2 os ................................ 88 program example of ei 2 os ................................ 97 watch timer interrupt and ei 2 os function ....... 281 ei 2 os descriptor configuration of ei 2 os descriptor (isd) ............. 82 ei 2 os status register ei 2 os status register (iscs) ............................. 85 .com .com .com .com 4 .com u datasheet
652 index eirr dtp/external interrupt factor register (eirr) ......................................................... 332 elvr detection level setting register (elvr) (high) ......................................................... 334 detection level setting register (elvr) (low) ......................................................... 335 enir dtp/external interrupt enable register (enir) ......................................................... 333 erase all data erase from flash memory (chip erase) ......................................................... 548 sector erase suspension in flash memory ......... 551 erase resumption erase resumption in flash memory .................. 552 erasing detailed explanation of programming and erasing flash memory .................. 544 erasing any data in flash memory (sector erasing) ......................................................... 549 programming and erasing flash memory .......... 528 erasing procedure erasing procedure for flash memory sectors ......................................................... 549 error node status transition due to error occurrence ......................................................... 445 event count mode event count mode .......................................... 244 operation in event count mode ....................... 267 program example in event count mode ............ 271 setting of event count mode ........................... 265 exception processing exception processing ......................................... 91 execution cycle count calculating the execution cycle count ............. 588 execution cycle count .................................... 587 extended i/o extended i/o area ............................................. 23 external clock baud rate by external clock ............................ 407 connection of oscillator and external clock ......................................................... 123 external interrupt external interrupt function .............................. 339 external reset block diagram of external reset pin ................ 103 f f 2 mc-16lx f 2 mc-16lx instruction list ............................ 594 factor correspondence of reset f actor bit and reset factor .........................................................107 notes on reset factor bit .................................107 fetch mode fetch .....................................................105 ff bank access to ff bank by rom mirroring function .........................................................524 flag change inhibit prefix flag change inhibit prefix (ncc) .......................56 flag set generation of receive interrupt and timing of flag set ........................397 generation of transmit interrupt and timing of flag set ........................399 flags hardware sequence flags .................................535 flash memory all data erase from flash memory (chip erase) .........................................................548 data programming to flash memory .................546 detailed explanation of programming and erasing flash memory ..................544 erase resumption in flash memory ..................552 erasing any data in flash memory (sector erasing) .........................................................549 erasing procedure for flash memory sectors .........................................................549 features of 512 kbit flash memory ...................528 list of registers and rese t values of flash memory .........................................................529 overview of 512 kbit flash memory .................528 program example of 512 kbit flash memory .........................................................553 programming and erasing flash memory ...........528 read/reset state in flash memory ....................545 sector configuration of 512 kbit flash memory .........................................................529 sector erase suspension in flash memory .........551 flash memory control status register flash memory control status register (fmcs) .........................................................530 flash microcontroller programmer connection example in single-chip mode (power supplied from flash microcontroller programmer) ......................................563 example of minimum connection to flash microcontroller programmer (power supplied from flash microcontroller programmer) ......................................567 example of minimum connection to flash microcontroller programmer (user power supply used) ...................565 .com .com .com .com 4 .com u datasheet
653 index flash microcontroller programmer system flash microcontroller programmer system configuration (made by yokogawa digital computer corporation) ........................560 fmcs flash memory control status register (fmcs) ..........................................................530 fpt-48p-m26 package dimension of fpt-48p-m26 ..................10 pin assignment (fpt-48p-m26) ...........................9 free-run timer block diagram of 16-bit free-run timer ............218 operation of 16-bit free-run timer ....................234 operation timing of 16-bit free-run timer ........235 setting of 16-bit free-run timer ........................234 frequency oscillation clock frequency and serial clock input frequency .........560 g general operation of port 3 (general - purpose i/o port) ..........................................................174 general-purpose i/o port block diagram of pins of port 2 (general-purpose i/o port) ...................167 operation of port 2 (general-purpose i/o port) ..........................................................169 general-purpose register configuration of general-purpose register ...........50 dedicated registers and general-purpose register ............................................................35 general-purpose register area and register bank pointer ......................45 generator baud rate by dedicated baud rate generator ..........................................................402 h handling devices precautions when handling devices ....................18 hardware interrupt hardware interrupt .............................................71 hardware interrupt inhibition ..............................72 mechanism of hardware interrupt .......................72 operation of hardware interrupt ..........................75 procedure for use of hardware interrupt ..............76 return from hardware interrupt ..........................74 start of hardware interrupt .................................74 hardware sequence flags hardware sequence flags .................................535 i i/o i/o area ........................................................... 23 i/o address pointer i/o address pointer (ioa) .................................. 84 i/o circuit i/o circuit ........................................................ 14 i/o port block diagram of pins of port 2 (general-purpose i/o port) .................. 167 i/o port function ............................................. 158 operation of port 2 (general-purpose i/o port) ......................................................... 169 operation of port 3 (gen eral - purpose i/o port) ......................................................... 174 registers of i/o ports ....................................... 160 icr bit configuration of interrupt control register (icr) ........................................................... 68 interrupt control register (icr00 to icr15) ........ 66 ics input capture control status registers (ics01 and ics23) ............................. 229 id register id register (idr) ............................................ 479 ide register ide register (ider) ........................................ 452 ider ide register (ider) ........................................ 452 idr id register (idr) ............................................ 479 ilm interrupt level mask register (ilm) ................... 46 image access image access to internal rom ........................... 25 independent operation mode setting for 8-bit ppg output 2-channel independent operation mode ............... 308 index interrupt vector index ...................................... 642 pin function index ........................................... 640 register index ................................................. 631 indirect addressing indirect addressing .......................................... 580 indirect-specifying addressing by indirect-specifying 32-bit register ........................................................... 28 input capture block diagram of input capture ....................... 220 operation of input capture ............................... 237 operation timing of input capture .................... 238 processing of progra m for measuring cycle using input capture ............................ 240 setting of input capture ................................... 236 .com .com .com .com 4 .com u datasheet
654 index input capture control status registers input capture control status registers (ics01 and ics23) ............................. 229 input capture data registers input capture data registers 0 to 3 (ipcp0 to ipcp3) ......................................................... 232 operation of input capture data registers 0 to 3 (ipcp0 to ipcp3) ............................... 232 input/output pins state of input/output pins (single-chip mode) ......................................................... 145 input/output timer 16-bit input/output timer interrupts and ei 2 os function ............................ 233 block diagram of 16-bit input/output timer ......................................................... 217 block diagram of pins for 16-bit input/output timer ......................................................... 222 configuration of 16-bit input/output timer ....... 216 correspondence between 16-bit input/output timer interrupt and ei 2 os ............................ 233 functions of 16-bit input/output timer ............. 216 generation of interrupt request from 16-bit input/output timer ................... 224 interrupt control bits an d interrupt factors of 16-bit input/output timer ................... 233 list of registers and reset values of 16-bit input/output timer ................... 223 pins of 16-bit input/output timer ..................... 222 precautions when 16-b it input/output timer ......................................................... 239 instruction description of instruction presentation items and symbols ....................................... 591 f 2 mc-16lx instruction list ............................ 594 prefix code and interrupt inhibit instruction ........ 57 instruction map structure of instruction map ............................. 609 instruction types instruction types ............................................. 571 internal clock mode internal clock mode ........................................ 244 operation in internal clock mode ..................... 261 program example in internal clock mode ......... 269 setting of internal clock mode ......................... 260 internal rom image access to internal rom ........................... 25 internal timer baud rate by internal timer (16-bit reload timer output) .............. 405 interrupt 16-bit input/output timer interrupts and ei 2 os function ............................ 233 8-/10-bit a/d converter interrupt and ei 2 os ......................................................... 364 8-/16-bit ppg timer interrupt and ei 2 os function .........................................................306 block diagram of dtp/external interrupt ..........329 cancellation of standby mode by interrupt ........146 correspondence between 16-b it input/output timer interrupt and ei 2 os ............................233 correspondence between 16-bit reload timer interrupt and ei 2 os ............................257 correspondence between 8-/16-bit ppg timer interrupt and ei 2 os ............................305 correspondence between ti mebase timer interrupt and ei 2 os ..........................................195 details of pins and interrupt numbers ................330 dtp/external interrupt function .......................328 dtp/external interrupt operation ......................337 external interrupt function ...............................339 generation of interrupt from 8-/10-bit a/d converter .........................................................353 generation of receive interrupt and timing of flag set ..............................................397 generation of transmit interrupt and timing of flag set ..............................................399 hardware interrupt .............................................71 hardware interrupt inhibition ..............................72 interrupt control bits and interrupt factors of 16-bit input/output timer ....................233 interrupt number .............................................321 interrupts of 16-bit reload timer ......................257 interrupts of 8-/16-bit ppg timer ......................305 interrupt of a/d converter ................................364 interrupts of can controller ............................484 interrupt of uart1 .........................................395 interrupt operation .............................................60 interrupt related to uart1 and ei 2 os .............396 list of registers and reset values in dtp/external interrupt ....................331 mechanism of hardware interrupt .......................72 multiple interrupts .............................................77 operation of hardware interrupt ..........................75 pins of dtp/external interrupt ..........................331 precautions when using dt p/external interrupt .........................................................341 procedure for use of hardware interrupt ..............76 program example of dtp/external interrupt function .........................................................343 registers and vector tables related to interrupt of can controller ..................................485 return from hardware interrupt ..........................74 setting of dtp/external interrupt ......................336 start and operation of software interrupt .............79 start of hardware interrupt .................................74 timebase timer interrupt .................................195 type and function of interrupt ............................59 watch timer interrupt ......................................281 watch timer interrupt and ei 2 os function ........281 .com .com .com .com 4 .com u datasheet
655 index interrupt control register bit configuration of interrupt control register (icr) ............................................................68 function of interrupt control register ..................69 interrupt control register (icr00 to icr15) ........66 interrupt control register list .............................64 interrupt factor,interrupt vector, and interrupt control register ................62 interrupt factor interrupt control bits an d interrupt factors of 16-bit input/output timer ....................233 interrupt factor,interrupt vector, and interrupt control register ................62 interrupt inhibit instruction prefix code and interrupt inhibit instruction .........57 interrupt level mask register interrupt level mask register (ilm) ...................46 interrupt number interrupt number .............................................321 interrupt processing program example of interrupt processing .............95 stack operation at return from interrupt processing ............................................................94 stack operation at star ting interrupt processing ............................................................94 time required to start interrupt processing .........92 interrupt request generation of interrupt request by can controller ..........................................................436 generation of interrupt request from 16-bit input/output timer ....................224 generation of interrupt request from 16-bit reload timer ............................250 generation of interrupt request from 8-/16-bit ppg timer ............................297 generation of interrupt request from timebase timer ..........................................................192 generation of interrupt request from watch timer ..........................................................278 interrupt request generation by uart1 ............384 interrupt vector interrupt factor,interrupt vector, and interrupt control register ................62 interrupt vector .................................................61 interrupt vector index interrupt vector index ......................................642 interval timer functions of interval timer ...............................188 interval timer function ....................196, 274, 282 ioa i/o address pointer (ioa) ..................................84 ipcp input capture data registers 0 to 3 (ipcp0 to ipcp3) ..........................................................232 operation of input capture data registers 0 to 3 (ipcp0 to ipcp3) ............................... 232 iscs ei 2 os status register (iscs) ............................. 85 isd configuration of ei 2 os descriptor (isd) ............. 82 l last event indicate register last event indicate register (leir) .................. 442 leir last event indicate register (leir) .................. 442 linear addressing linear addressing and bank addressing .............. 27 linear addressing by specifying 24-bit operand ........................................................... 28 lineup product lineup for mb90385 series ...................... 5 list list of registers and reset values of 16-bit reload timer ............................ 249 low-power consumption block diagram of low-power consumption circuit ......................................................... 127 low-power consumption mode control register low-power consumption mode control register (lpmcr) ........................................... 130 low-power consumption mode control register and reset values ................................ 129 notes on accessing the low-power consumption mode control register (lpmcr) to enter the standby mode ............................... 148 lpmcr low-power consumption mode control register (lpmcr) ........................................... 130 notes on accessing the low-power consumption mode control register (lpmcr) to enter the standby mode ............................... 148 m machine clock machine clock ................................................ 119 master/slave type communication master/slave type communication function ......................................................... 420 mb90385 series block diagram of mb90385 series ....................... 8 cpu and resources for mb90385 series ............... 6 features of mb90385 series ................................. 2 memory map for mb90385 series ...................... 24 product lineup for mb90385 series ...................... 5 .com .com .com .com 4 .com u datasheet
656 index mb90f387/s basic configuration of serial programming connection for mb90f387/s ............... 558 md continuous conversion mode (adcs: md1,md0= "10 b ") ............... 365 pause-conversion mode (adcs: md1,md0= "11 b ") ......................................................... 365 setting of mode pins (md2 to md0) ................ 150 single conversion mode (adcs: md1,md0= "00 b " or "01 b " ) ................................. 365 memory access mode selection of memory access mode ................... 155 memory map e 2 prom memory map ................................... 517 memory map .................................................... 26 memory map for mb90385 series ...................... 24 system configuration and e 2 prom memory map ......................................................... 516 memory space memory space .................................................. 22 memory space when ro m mirroring function enabled/disabled ............................... 525 message buffer caution for disabling message buffers by bval bits ......................................................... 503 message buffers .............................................. 478 procedure for receiving message buffer (x) ......................................................... 498 procedure for transmittin g message buffer (x) ......................................................... 495 setting configuration of multiple message buffer ......................................................... 501 message buffer valid register message buffer valid register (bvalr) .......... 450 minimum connection example of minimum connection to flash microcontroller programmer (power supplied from flash microcontroller programmer) ...................................... 567 example of minimum connection to flash microcontroller programmer (user power supply used) .................. 565 mode block diagram of port 1 pins (in single chip mode) ......................................................... 162 bus mode ....................................................... 154 cancellation of standby mode by interrupt ........ 146 classification of modes ................................... 149 clock mode ............................................ 118, 125 connection example in single-chip mode (power supplied from flash microcontroller programmer) ...................................... 563 connection example in single-chip mode (user power supply used) .................. 561 continuous conversion mode (adcs: md1,md0= "10 b ") ................365 conversion modes of 8-/10-bit a/d converter .........................................................348 cpu intermittent operation mode .....................125 cpu operation modes and current consumption .........................................................124 notes on accessing the low-power consumption mode control register (lpmcr) to enter the standby mode ...............................148 event count mode ...........................................244 function of registers for port 1 (in single chip mode) .........................................................163 internal clock mode ........................................244 mode pin ........................................................104 note on cancelling standby mode ....................146 notes on the transition to standby mode ...........146 operating state in each standby mode ..............134 operation in asynchronous mode .....................410 operation in clock synchronous mode (operation mode 2) .............................415 operation in cpu intermittent operation mode .........................................................133 operation in event count mode ........................267 operation in internal clock mode .....................261 operation mode ...............................................149 operation modes of 16-bit reload timer ...........244 operation modes of 8-/16-bit ppg timer ...........286 operation of continuous conversion mode ........368 operation of pause-conversion mode .................370 operation of port 1 (in single chip mode) .........164 operation of single conversion mode ...............366 oscillation stabilization wait time in standby mode .........................................................104 pause-conversion mode (adcs: md1,md0= "11 b ") .........................................................365 program example in event count mode ............271 program example in internal clock mode ..........269 registers for port 1 (in single chip mode) .........162 return from sleep mode ...................................136 return from stop mode ....................................142 return from timebase timer mode ...................140 return from watch mode ..................................138 selection of memory access mode ...................155 setting for 16-bit ppg output operation mode .........................................................310 setting for 8+8-bit ppg output operation mode .........................................................313 setting for 8-bit ppg output 2-channel independent operation mode ...............308 setting of continuous conversion mode ............368 setting of event count mode ............................265 setting of internal clock mode .........................260 setting of pause-conversion mode .....................370 setting of single conversion mode ...................366 single conversion mode (adcs: md1,md0= "00 b " or "01 b ") ...................................365 .com .com .com .com 4 .com u datasheet
657 index standby mode .................................................125 state of input/output pins (single-chip mode) ..........................................................145 stop mode .......................................................141 transition of clock mode .........................118, 147 transition to sleep mode ..................................135 transition to standby mode ..............................146 transition to timebase timer mode ..................139 transition to watch mode .................................137 mode data mode data ......................................................152 setting mode data ...........................................153 state of pins after mode data read ....................108 mode fetch mode fetch .....................................................105 mode pins setting mode pins ............................................151 setting of mode pins (md2 to md0) .................150 multi-byte data access to multi-byte data ...................................32 storage of multi-byte data in stack .....................32 store of multi-byte data in ram ........................31 multi-byte length storage of multi-byte length operand .................31 multiple interrupts multiple interrupts .............................................77 multiple message buffer setting configuration of multiple message buffer ..........................................................501 multiplication rate selection of pll clock multiplication rate .......119 n ncc flag change inhibit prefix (ncc) .......................56 node status transition node status transition due to error occurrence ..........................................................445 o operand linear addressing by specifying 24-bit operand ............................................................28 storage of multi-byte length operand .................31 operating state setting and operating state ...............................518 operation clock supply of operation clock ................................199 operation mode cpu intermittent operation mode .....................125 cpu operation modes and current consumption ..........................................................124 operation in cpu intermittent operation mode ......................................................... 133 operation mode .............................................. 149 operation modes of 16-bit reload timer ........... 244 setting for 8-bit ppg output 2-channel independent operation mode ............... 308 operation mode control register ppg0 operation mode control register (ppgc0) ......................................................... 298 ppg1 operation mode control register (ppgc1) ......................................................... 300 oscillation clock frequency oscillation clock frequency and serial clock input frequency ......... 560 oscillation stabilization wait time operation as oscillation stabilization wait time timer ................................................ 197 operation during oscillation stabilization wait time ......................................................... 122 oscillation stabilization wait time ................... 147 oscillation stabilization wait time in standby mode ......................................................... 104 oscillation stabilization wait time timer of subclock ............................................ 283 reset sources and oscillation stabilization wait time ......................................................... 101 oscillator connection of oscillator and external clock ...... 123 p package dimension package dimension of fpt-48p-m26 .................. 10 pacsr address detection control register (pacsr) ......................................................... 511 padr detect address setting registers (padr0 and padr1) ......................... 513 patch operation of address match detection function at storing patch program in e 2 prom ......................................................... 519 patch processing flow of patch processing ................................. 520 pause-conversion mode operation of pause-conversion mode ................ 370 pause-conversion mode (adcs: md1,md0= "11 b ") ......................................................... 365 setting of pause-conversion mode .................... 370 pc program counter (pc) ........................................ 47 pcb bank select prefix (pcb,dtb,adb,spb) ........... 53 program bank register (pcb) ............................ 49 .com .com .com .com 4 .com u datasheet
658 index pin assignment pin assignment (fpt-48p-m26) ........................... 9 pin assignment of port 1 ................................. 161 pin assignment of port 2 ................................. 166 pin assignment of port 3 ................................. 171 pin assignment of port 4 ................................. 176 pin assignment of port 5 ................................. 181 pin description pin description ................................................. 11 pin function index pin function index .......................................... 640 pll clock multiplication rate selection of pll clock multiplication rate ....... 119 port 1 block diagram of port 1 pins (in single chip mode) ......................................................... 162 configuration of port 1 .................................... 161 function of registers for port 1 (in single chip mode) ......................................................... 163 operation of port 1 (in single chip mode) ......... 164 pin assignment of port 1 ................................. 161 registers for port 1 (in single chip mode) ........ 162 port 2 block diagram of pins of port 2 (general-purpose i/o port) .................. 167 configuration of port 2 .................................... 166 function of registers for port 2 ........................ 168 operation of port 2 (general-purpose i/o port) ......................................................... 169 pin assignment of port 2 ................................. 166 registers for port 2 .......................................... 167 port 3 block diagram of pins of port 3 ....................... 172 configuration of port 3 .................................... 171 function of registers for port 3 ........................ 173 operation of port 3 (general - purpose i/o port) ......................................................... 174 pin assignment of port 3 ................................. 171 registers for port 3 .......................................... 172 port 4 block diagram of pins of port 4 ....................... 177 configuration of port 4 .................................... 176 function of registers for port 4 ........................ 178 operation of port 4 .......................................... 179 pin assignment of port 4 ................................. 176 registers for port 4 .......................................... 177 port 5 block diagram of pins of port 5 ....................... 182 configuration of port 5 .................................... 181 function of registers for port 5 ........................ 183 operation of port 5 .......................................... 185 pin assignment of port 5 ................................. 181 registers for port 5 .......................................... 182 power supply connection example in single-chip mode (user power supply used) ...................561 connection example in single-chip mode (power supplied from flash microcontroller programmer) ......................................563 example of minimum connection to flash microcontroller programmer (power supplied from flash microcontroller programmer) ......................................567 example of minimum connection to flash microcontroller programmer (user power supply used) ...................565 ppg channels and ppg pins of ppg timers ..............289 ppg0 operation mode control register (ppgc0) .........................................................298 ppg0/1 count clock select register (ppg01) .........................................................302 ppg1 operation mode control register (ppgc1) .........................................................300 ppg output setting for 8-bit ppg output 2-channel independent operation mode ...............308 ppg output operation mode setting for 16-bit ppg output operation mode .........................................................310 setting for 8+8-bit ppg output operation mode .........................................................313 ppg reload registers ppg reload registers (prll0/prlh0,prll1/prlh1) .........304 ppg timer 8-/16-bit ppg timer interrupt and ei 2 os function .........................................................306 block diagram of 8-/16-bit ppg timer 0 ...........290 block diagram of 8-/16-bit ppg timer 1 ...........293 block diagram of 8-/16-bit ppg timer pins .........................................................296 channels and ppg pins of ppg timers ..............289 correspondence between 8-/16-bit ppg timer interrupt and ei 2 os ............................305 functions of 8-/16-bit ppg timer ......................286 generation of interrupt request from 8-/16-bit ppg timer ............................297 interrupts of 8-/16-bit ppg timer ......................305 list of registers and reset values of 8-/16-bit ppg timer ............................297 operation modes of 8-/16-bit ppg timer ...........286 operation of 8-/16-bit ppg timer .....................307 pins of 8-/16-bit ppg timer ..............................296 precautions when using 8-/16-bit ppg timer .........................................................316 ppgc ppg0 operation mode control register (ppgc0) .........................................................298 .com .com .com .com 4 .com u datasheet
659 index ppg1 operation mode c ontrol register (ppgc1) ..........................................................300 prefix bank select prefix (pcb,dtb,adb,spb) ............53 common register bank prefix (cmr) .................55 flag change inhibit prefix (ncc) .......................56 prefix code array of prefix codes .........................................58 prefix code .......................................................52 prefix code and interrupt inhibit instruction .........57 presentation items description of instruction presentation items and symbols .......................................591 presetting presetting ........................................................494 prlh ppg reload registers (prll0/prlh0,prll1/prlh1) .........304 prll ppg reload registers (prll0/prlh0,prll1/prlh1) .........304 processing exception processing .........................................91 program example of interrupt processing .............95 stack operation at return from interrupt processing ............................................................94 stack operation at star ting interrupt processing ............................................................94 time required to start interrupt processing .........92 processing time ei 2 os processing time (time for one transfer) ............................................................89 processor status configuration of processor status (ps) .................42 product lineup product lineup for mb90385 series ......................5 program operation of address match detection function at storing patch program in e 2 prom ..........................................................519 processing of program for measuring cycle using input capture ............................240 program execution ...........................................515 program bank register program bank register (pcb) .............................49 program counter program counter (pc) ........................................47 program example program example for address match detection function .............................................521 program example for uart1 ...........................424 program example in event count mode ............271 program example in internal clock mode ..........269 program example of 512 kbit flash memory ......................................................... 553 program example of can transmission and reception ..................................... 504 program example of delayed interrupt generation module ............................. 326 program example of dtp function ................... 344 program example of dtp/external interrupt function ......................................................... 343 program example of ei 2 os ................................ 97 program example of interrupt processing ............ 95 program example of timebase timer ................ 201 program example of watch timer .................... 284 program example of watchdog timer ............... 214 programming data programming procedure ........................... 546 data programming to flash memory ................. 546 detailed explanation of programming and erasing flash memory .................. 544 programming and erasing flash memory .......... 528 protection a/d-converted data protection function in 8-/10-bit a/d converter ................... 373 ps configuration of processor status (ps) ................ 42 r ram ram area ........................................................ 23 store of multi-byte data in ram ........................ 31 rcr reception complete register (rcr) ................. 466 read read/reset state in flash memory .................... 545 receive interrupt generation of receive interrupt and timing of flag set ............................................. 397 receive/transmit error counter receive/transmit error counter (rtec) ........... 444 receiving procedure for receiving message buffer (x) ...... 498 reception program example of can transmission and reception ..................................... 504 reception ........................................................ 490 reception complete interrupt enable register reception complete interrupt enable register (rier) ......................................................... 472 reception complete register reception complete register (rcr) ................. 466 reception overrun register reception overrun register (rovrr) .............. 470 reception rtr register reception rtr register (rrtrr) .................... 468 .com .com .com .com 4 .com u datasheet
660 index register bank register bank ................................................... 51 register bank pointer general-purpose register area and register bank pointer ..................... 45 register bank pointer (rp) ................................ 45 register index register index ................................................. 631 reload registers 16-bit reload registers (tmrlr0,tmrlr1) ......................................................... 256 reload timer baud rate by internal timer (16-bit reload timer output) .............. 405 block diagram for pins of 16-bit reload timer ......................................................... 248 block diagram of 16-bit reload timer .............. 246 correspondence between 16-bit reload timer interrupt and ei 2 os ............................ 257 ei 2 os function of 16-bit reload timer ............. 257 generation of interrupt request from 16-bit reload timer ........................... 250 interrupts of 16-bit reload timer ...................... 257 list of registers and reset values of 16-bit reload timer ........................... 249 operation modes of 16-bit reload timer ........... 244 pins of 16-bit reload timer ............................. 248 precautions when using 16-bit reload timer ......................................................... 268 setting of 16-bit reload timer ......................... 258 remote frame receiving wait register remote frame receiving wait register (rfwtr) ......................................................... 458 reset block diagram of external reset pin ................ 103 flowchart of reset operation ........................... 104 list of registers and reset values in delayed interrupt generation module ............... 322 list of registers and reset values in dtp/external interrupt .................... 331 list of registers and reset values of 16-bit input/output timer ................... 223 list of registers and reset values of 16-bit reload timer ........................... 249 list of registers and reset values of 8-/10-bit a/d converter ...................... 353 list of registers and reset values of 8-/16-bit ppg timer ........................... 297 list of registers and reset values of address match detection function ......................................................... 510 list of registers and reset values of flash memory ......................................................... 529 list of registers and reset values of rom mirroring function select module ......................................................... 525 list of registers and reset values of timebase timer .........................................................192 list of registers and rese t values of watch timer .........................................................278 list of registers and reset values of watchdog timer .........................................................207 low-power consumption mode control register and reset values ................................129 read/reset state in flash memory ....................545 register in clock generation section and list of reset values .......................................114 reset factor bit ...............................................106 reset factors .....................................................99 reset sources and oscillation stabilization wait time .........................................................101 state of pins at reset ........................................108 reset factor correspondence of reset f actor bit and reset factor .........................................................107 notes on reset factor bit .................................107 reset factor bit ...............................................106 reset factors .....................................................99 reset sources reset sources and oscillation stabilization wait time .........................................................101 reset state read/reset state in flash memory ....................545 resources cpu and resources for mb90385 series ...............6 rfwtr remote frame receiving wait register (rfwtr) .........................................................458 rier reception complete interrupt enable register (rier) .........................................................472 rom rom area ........................................................23 rom mirror function select register rom mirror function select register (romm) .........................................................526 rom mirroring function access to ff bank by rom mirroring function .........................................................524 memory space when rom mirroring function enabled/disabled ................................525 rom mirroring functi on select module block diagram of rom mirroring function select module ..............................................524 list of registers and reset values of rom mirroring function select module .........................................................525 romm rom mirror function select register (romm) .........................................................526 .com .com .com .com 4 .com u datasheet
661 index rovrr reception overrun register (rovrr) ..............470 rp register bank pointer (rp) .................................45 rrtrr reception rtr register (rrtrr) ....................468 rtec receive/transmit error counter (rtec) ...........444 s scr serial control register 1 (scr1) .......................385 sector erasing procedure for flash memory sectors ..........................................................549 sector configuration of 512 kbit flash memory ..........................................................529 sector configuration sector configuration of 512 kbit flash memory ..........................................................529 sector erase suspension sector erase suspension in flash memory .........551 sector erase timer flag sector erase timer flag (dq3) .........................541 sector erasing erasing any data in flash memory (sector erasing) ..........................................................549 segment definition of bit timing segment ......................447 serial clock input frequency oscillation clock frequency and serial clock input frequency .........560 serial control register serial control register 1 (scr1) .......................385 serial input data register serial input data register 1 (sidr1) .................391 serial mode register serial mode register 1 (smr1) .........................387 serial output data register serial output data register 1 (sodr1) .............392 serial programming connection basic configuration of serial programming connection for mb90f387/s ...............558 serial status register serial status register 1 (ssr1) .........................389 setting setting of internal clock mode ..........................260 sidr serial input data register 1 (sidr1) .................391 single chip mode block diagram of port 1 pins (in single chip mode) ..........................................................162 connection example in single-chip mode (power supplied from flash microcontroller programmer) ...................................... 563 connection example in single-chip mode (user power supply used) ................... 561 function of registers for port 1 (in single chip mode) ......................................................... 163 operation of port 1 (in single chip mode) ......... 164 registers for port 1 (in single chip mode) ......... 162 state of input/output pins (single-chip mode) ......................................................... 145 single conversion mode operation of single conversion mode ............... 366 setting of single conversion mode ................... 366 single conversion mode (adcs: md1,md0= "00 b " or "01 b ") .................................. 365 sleep mode return from sleep mode .................................. 136 transition to sleep mode ................................. 135 smr serial mode register 1 (smr1) ........................ 387 sodr serial output data register 1 (sodr1) ............. 392 software interrupt return from software interrupt ........................... 79 start and operation of software interrupt ............. 79 spb bank select prefix (pcb,dtb,adb,spb) ........... 53 ssb user stack bank register (usb) and system stack bank register (ssb) ........................................................... 49 ssp system stack pointer (ssp) ................................ 40 ssr serial status register 1 (ssr1) ......................... 389 stack stack area ........................................................ 41 stack operation at return from interrupt processing ........................................................... 94 stack operation at star ting interrupt processing ........................................................... 94 stack selection .................................................. 39 storage of multi-byte data in stack ..................... 32 standby mode cancellation of standby mode by interrupt ........ 146 notes on accessing the low-power consumption mode control register (lpmcr) to enter the standby mode ............................... 148 note on cancelling standby mode .................... 146 notes on the transition to standby mode ........... 146 operating state in each standby mode .............. 134 oscillation stabilization wait time in standby mode ......................................................... 104 standby mode ................................................. 125 .com .com .com .com 4 .com u datasheet
662 index transition to standby mode ............................. 146 start interrupt processing time required to start interrupt processing ......... 92 starting interrupt processing stack operation at star ting interrupt processing ........................................................... 94 state read/reset state in flash memory .................... 545 state transition diagram state transition diagram ................................. 144 status transition node status transition due to error occurrence ......................................................... 445 stop mode return from stop mode ................................... 142 stop mode ...................................................... 141 storing patch program operation of address match detection function at storing patch program in e 2 prom ......................................................... 519 subclock oscillation stabilization wait time timer of subclock ........................................... 283 supply map clock supply map ........................................... 110 symbols description of instruction presentation items and symbols ....................................... 591 synchronous mode operation in clock synchronous mode (operation mode 2) ............................ 415 system configuration system configuration and e 2 prom memory map ......................................................... 516 system stack bank register user stack bank register (usb) and system stack bank register (ssb) ........................................................... 49 system stack pointer system stack pointer (ssp) ................................ 40 t tbtc timebase timer control register (tbtc) ......... 193 tcanr transmission cancel register (tcanr) ........... 460 tccs timer counter control status register (tccs) ......................................................... 225 tcdt count operation of timer counter data register (tcdt) ............................................. 227 timer counter data register (tcdt) ............... 227 tcr transmission complete register (tcr) .............462 tier transmission complete interrupt enable register (tier) ...............................................464 timebase timer block diagram of timebase timer ....................190 correspondence between ti mebase timer interrupt and ei 2 os ..........................................195 generation of interrupt request from timebase timer .........................................................192 list of registers and reset values of timebase timer .........................................................192 precautions when using timebase timer ...........200 program example of timebase timer ................201 timebase timer interrupt .................................195 timebase timer control register timebase timer control register (tbtc) .........193 timebase timer mode return from timebase timer mode ...................140 transition to timebase timer mode ..................139 timer control status registers timer control status registers (high) (tmcsr0: h,tmcsr1: h) .................251 timer control status registers (low) (tmcsr0: l,tmcsr1: l) ..................253 timer counter control status register timer counter control st atus register (tccs) .........................................................225 timer counter data register count operation of timer counter data register (tcdt) ..............................................227 timer counter data register (tcdt) ................227 timer registers 16-bit timer registers (tmr0,tmr1) ..............255 timing limit over flag timing limit over flag (dq5) .........................540 tmcsr timer control status registers (high) (tmcsr0: h,tmcsr1: h) .................251 timer control status registers (low) (tmcsr0: l,tmcsr1: l) ..................253 tmr 16-bit timer registers (tmr0,tmr1) ..............255 tmrlr 16-bit reload registers (tmrlr0,tmrlr1) .........................................................256 toggle bit flag toggle bit flag (dq2) .....................................542 toggle bit flag (dq6) .....................................539 transfer ei 2 os processing time (time for one transfer) ...........................................................89 .com .com .com .com 4 .com u datasheet
663 index transition node status transition due to error occurrence ..........................................................445 notes on the transition to standby mode ...........146 state transition diagram ..................................144 transition of clock mode .................................147 transition to sleep mode ..................................135 transition to standby mode ..............................146 transition to timebase timer mode ..................139 transition to watch mode .................................137 transmission program example of can transmission and reception .....................................504 transmission ...................................................487 transmission cancel register transmission cancel register (tcanr) ............460 transmission complete interrupt enable register transmission complete interrupt enable register (tier) ...............................................464 transmission complete register transmission complete register (tcr) .............462 transmission request register transmission request register (treqr) ...........454 transmission rtr register transmission rtr register (trtrr) ...............456 transmit interrupt generation of transmit interrupt and timing of flag set ..............................................399 transmitting procedure for transmitti ng message buffer (x) ..........................................................495 treqr transmission request register (treqr) ...........454 trtrr transmission rtr register (trtrr) ...............456 u uart1 block diagram of pins of uart1 .....................383 block diagram of uart1 ................................380 ei 2 os function of uart1 ...............................396 function of uart1 .........................................378 interrupt of uart1 ..........................................395 interrupt related to uart1 and ei 2 os .............396 interrupt request generation by uart1 ............384 list of registers in uart1 ...............................383 operation of uart1 ........................................408 precautions when using uart1 .......................423 program example for uart1 ...........................424 select of uart1 baud rate .............................400 uart1 pin .....................................................383 underflow operation at underflow ....................................245 underflows operation as 16-bit time r register underflows ................................................. 261, 266 usb user stack bank register (usb) and system stack bank register (ssb) ........................................................... 49 user power supply example of minimum connection to flash microcontroller programmer (user power supply used) ................... 565 connection example in single-chip mode (user power supply used) ................... 561 user stack bank register user stack bank register (usb) and system stack bank register (ssb) ........................................................... 49 user stack pointer user stack pointer (usp) ................................... 40 usp user stack pointer (usp) ................................... 40 v vector tables registers and vector tables related to interrupt of can controller .................................. 485 w watch mode return from watch mode ................................. 138 transition to watch mode ................................ 137 watch timer block diagram of watch timer ........................ 276 generation of interrupt request from watch timer ......................................................... 278 list of registers and rese t values of watch timer ......................................................... 278 program example of watch timer .................... 284 watch timer counter ....................................... 282 watch timer interrupt ...................................... 281 watch timer interrupt and ei 2 os function ....... 281 watch timer control register watch timer control register (wtc) ............... 279 watchdog timer block diagram of watchdog timer ................... 205 functions of watchdog timer ........................... 204 list of registers and reset values of watchdog timer ......................................................... 207 operation of watchdog timer .......................... 210 precautions when using watchdog timer .......... 213 program example of watchdog timer ............... 214 setting operation clock of watchdog timer ......................................................... 283 .com .com .com .com 4 .com u datasheet
664 index watchdog timer control register watchdog timer control register (wdtc) ....... 208 wdtc watchdog timer control register (wdtc) ....... 208 wtc watch timer control register (wtc) ............... 279 .com .com .com .com 4 .com u datasheet
cm44-10118-2e fujitsu semiconductor ? controller manual f 2 mc tm -16lx 16-bit microcontroller mb90385 series hardware manual november 2005 the second edition published fujitsu limited electronic devices edited business promotion dept. .com .com .com .com 4 .com u datasheet
.com .com .com 4 .com u datasheet
